Reference cell with various load circuits compensating for...

Details Reference cell with various load circuits compensating for... Reference cell with various load circuits compensating for...

2002-09-16

2004-06-22

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185240

Reexamination Certificate

active

06754106

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to a reference cell with various load circuits compensating for corresponding source side loading effects when reading non-volatile memory.
BACKGROUND ART
A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for non-volatile data storage.
A typical configuration of a flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (Si
x
O
y
). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
The flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
Prior Art
FIG. 1
is a circuit diagram of a portion of an array
100
of memory cells arranged in a NOR type of configuration. The array
100
contains non-volatile flash memory cells arranged in rows and columns. A plurality of word lines
110
, or select lines, are coupled to a plurality of rows of memory cells. The plurality of word lines
110
include WL
1
, WL
2
, WL
3
, and WL
4
. Each of the plurality of word lines
110
are coupled to gate regions of memory cells in their respective rows. For example, WL
1
is coupled to gate regions of memory cells defined by WL
1
-BL
1
, WL
1
-BL
2
, WL
1
-BL
3
, and WL
1
-BL
4
, etc.
In addition, a plurality of bit lines
120
are coupled to a plurality columns of memory cells. The plurality of bit lines
120
include BL
1
, BL
2
, BL
3
, and BL
4
. The plurality of bit lines are coupled to drain regions of memory cells in their respective columns. For example, BL
1
is coupled to drain regions of memory cells defined by WL
1
-BL
1
, WL
2
-BL
1
, WL
3
-BL
1
, and WL
4
-BL
1
.
In the array
100
of memory cells, a particular memory cell can be identified and read to determine if the cell is programmed or erased by applying the correct voltages to a corresponding bit line and word line. For example, in order to read the memory cell
140
, appropriate voltages would be applied to bit line BL
2
and word line WL
2
to read the state of memory cell
140
. Correspondingly, in order to read the memory cell
150
, appropriate voltages would be applied to bit line BL
4
and word line WL
2
to read the state of memory cell
150
.
A plurality of source lines
130
are coupled to each of the rows of memory cells. The plurality of source lines include SL
1
, SL
2
, SL
3
, and SL
4
. Each of the plurality of source lines
130
are coupled to source regions of memory cells in their respective rows. For example, SL
1
is coupled to source regions of memory cells defined by WL
1
-BL
1
, WL
1
-BL
2
, WL
1
-BL
3
, and WL
1
-BL
4
, etc.
The plurality of source lines
130
are used to read current from identified memory cells in the array
100
of memory cells. For example, in order to determine the state of memory cell
140
, appropriate voltages are applied to BL
2
and WL
2
. When selected and activated, the memory cell
140
will produce a current through its respective source region that is read from an source line node
132
corresponding to its respective source line, SL
2
. Correspondingly, source line SL
1
is coupled to source line node
131
, SL
3
is coupled to source line node
133
, and SL
4
is coupled to source line node
134
.
Thereafter, the current from memory cell
140
is compared to a reference current of an approximately identical memory cell to determine its state, whether it is programmed (0) or erased (1). If the current from memory cell
140
is less than the reference current, then the memory cell
140
is in a programmed state (0), and its corresponding threshold voltage (V
T
) is very high and should be higher than the threshold voltage of the reference cell (V
TRef
). Correspondingly, if the current from memory cell
140
is more than the reference current, then the memory cell
140
is in an erased state (1), and its corresponding V
T
should be lower than V
TRef
.
A problem with source side loading effects exists when reading memory cells in a row of memory cells in the array
100
of memory cells. For flash memory technology, the cells in an array
100
are erased simultaneously. After the erase process, the threshold voltage for each cell is checked individually. Current from each of the individual memory cells in the array
100
is compared to current from the reference cell to determine if the memory cell has been erased.
For NOR type flash configurations, the source lines are formed by implantation on silicon. As a material, silicon has a high unit resistance value. Since the resistance is relatively high, there are some source side loading effects. In particular, the resistance value of a particular source line increases as more and more of the source line is used to access memory cells along a row of memory cells.
Since the array is laid out more or less uniformly, the same distance of source line connects source regions of adjoining memory cells in a row of memory cells. That distance can be associated with a unit source side resistance value (R
s
). For example, in the row of memory cells identified by SL
2
, the source side resistance for each of the memory cells is approximately as follows, in the following format, memory cell;resistance value: WL
2
-BL
1
;R
s
, WL
2
-BL
2
;2R
s
, WL
2
-BL
3
;3R
s
, and WL
2
-BL
4
;4R
s
.
Moreover, the source side loading effect will cause variation in the threshold voltages in a row of memory cells based on the location of the memory cell being accessed. For example, assuming that all the bits or memory cells in the array
100
of memory cells have the same approximate true V
T
, when the same voltage is applied to respective word lines and bit lines, the same current and threshold voltage should approximately be read no matter the location of the memory device in the array
100
, and in particular, along a single row of memory cells in the array
100
.
However, because of the source side loading effects, the threshold voltage will increase the further away from the source line node of the respective source line from which the current is read. For example, for bit (WL
2
-BL
4
), the source side resistance is equal to 4R
s
, and the corresponding voltage increase for its threshold voltage would be equal to 4R
s
times the current. For bit (WL
2
-BL
2
), the source side resistance is less and is equal to 2R
s
, and the corresponding voltage increase for its threshold voltage would be equal to 2R
s
times the current.
Since the voltage drop at the source side for bits (WL
2
-BL
4
and WL
2
-BL
2
) are different, even though the true V
T
is approximately identical for the bits (WL
2
-BL
4
and WL
2
-BL
2
), during a read operation, the bit (WL
2
-BL
2
) will read more current because of lower

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