Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-21
2002-06-25
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S210130
Reexamination Certificate
active
06411549
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to sense amplifiers for use with nonvolatile semiconductor memories. More specifically, it relates to the structure of a reference memory cell used in establishing a reference voltage for a sense amplifier.
BACKGROUND ART
Within a memory IC, sense amplifiers are used to read data from a target memory cell within a memory array. These amplifiers are typically categorized as single-ended sense amplifiers or differential sense amplifier. Single-ended sense amplifiers are commonly used in memories having a single-bit per memory cell. Examples of single-bit per cell memories are EEPROM and Flash EPROMs. These single-bit per cell memories store only one of the true value or compliment value of a datum item in each memory cell. This is in contrast to dual-bit per cell memories such as SRAMs, which store both the true and complement value of a datum item in each memory cell. Having both the true and complement value of a datum item within each memory cell facilitates and speeds up the reading of a memory cell since one can identify the stored datum item by simultaneously accessing both true and complement bits and simply determining which has the higher voltage potential. Stated more clearly, SRAMs use differential amplifiers to read each memory cell, and identify the logic state stored within a memory cell as soon as the direction of the voltage imbalance, representative of the true and complimentary data stored within the memory cell, is determined. Since single-bit per cell memories do not have the luxury of knowing the compliment of the stored datum item, their single-ended sensing circuitry requires a different, and more critically balanced approach.
Use of a differential sense amplifier in a nonvolatile memory would provide a big boost in reading speed, but would require two memory storage devices per memory cell, one for the true data and another for the complement data. This would reduce the memory capacity at least by 50%. It is more likely that the reduction would be much greater because of the need to accommodate additional bitlines, equalization circuitry, more complex program and erase circuitry, and other circuitry required to implement a dual-bit per memory cell architecture. Therefore, nonvolatile memories generally use single-ended sense amplifiers.
With reference to
FIG. 1
, a single-ended sensing circuit
12
suitable for use with a single-bit memory cell is shown
14
. Target single-bit memory cell
14
is depicted as a single floating gate transistor
16
. Sensing circuit
12
determines the logic state stored within target memory cell
14
by sensing a potential difference between a sense line
18
coupled to target memory cell
14
and a reference line
20
coupled to a reference memory cell
22
. The potential of sense line
18
is dependent on the logic state, high or low, of the datum stored within target memory cell
14
. Typically, if the potential of sense line
18
is higher than that of reference line
20
, then target memory cell
14
is read as having a logic low state, and if the potential of sense line
18
is lower than reference line
20
, then target memory cell
14
is read as having a logic high state. Therefore, it is important that the voltage potential of reference line
20
be maintained at a value intermediate the logic high and logic low voltage potentials of target cell
14
.
At first glance, it would appear that the reference voltage on line
20
could be produced with a constant voltage generator, but this is not preferred. The potential at sense line
18
is affected not only by the potential at the gate of floating gate transistor
16
, but also by the architecture of the memory. The capacitive loads of target memory cell
14
depend on its physical structure and on its location within a larger memory array. These capacitive loads, in turn, affect the current sourcing capability of target memory cell
14
and thereby the potential at sense line
18
.
Therefore, an effort is made to help reference line
20
reflect these capacitive loads in order to better track the logic high and logic low voltages of target memory cell
16
. A typical method of tracking these effects on the logic high and logic low voltages of a target memory cell is to use another memory cell, i.e. a reference memory cell
22
, to produce the voltage potential for reference line
20
. The idea is that since the reference memory cell
22
hag a similar structure as target memory cell
14
, its behavior will be similar to that of target cell
14
. The potential of reference line
20
is therefore dependent on the current sourcing value of reference cell
22
.
Various methods of using a reference cell for producing the reference voltage for use with a single-ended sensing circuit are known in the art. Some of these methods are discussed in U.S. Pat. No. 5,572,474 to Sheen et al., U.S. Pat. No. 5,608,679 to Medlock et al., and U.S. Pat. No. 5,642,308 to Yoshida.
Applicants have found, however, that existing methods of generating a reference voltage on reference line
20
are not stable over the life of the memory IC. This is in part due to reference cell
22
using a floating gate transistor
26
to produce the reference voltage. Although using a floating gate transistor
26
within reference cell
22
is advantageous because it provides a better balance with the floating gate transistor
16
of target memory cell
14
, floating gate transistor
26
introduces additional problems that may complicate generating an accurate reference voltage on reference line
20
.
Since the threshold voltage of reference cell
22
should not changed, reference cell
22
is isolated from program and erase circuitry used in altering the state of the storage memory cells
14
in a main memory array. Reference memory cells, in general, are constructed with no charge on their floating gate
28
, and the charge level on their floating gate
28
is not intended to change since they are not connected to any programming or erasing circuitry. If desired, the threshold voltage level of reference cells may be adjusted by adjusting the substrate doping concentration of their channel region.
Unfortunately, there are several factors that can alter the charge level of a reference cell's floating gate
28
. Floating gate transistors, in general, are susceptible to read disturb problems that can change the amount of charge on a reference cell's floating gate
28
, which results in a change in its threshold voltage. This can result in a change in the cell's reference current value, which in turn changes the voltage value of reference line
20
. Due to the critical balancing of the sensing circuit
12
, a voltage change in sense line
20
can, at best, slow down sensing circuit
12
, and at worst, cause it to read erroneous data.
Additionally, Applicants have identified another source of error associated with the use of a floating gate reference cell
22
. The manufacturing of nonvolatile memory ICs often requires the use of plasmas. Plasma has an intrinsic electric charge associate with it that will typically alter the charge on the floating gate of a nonvolatile memory cell during the manufacturing process. To accommodate for this change in the floating gate charge, the main memory array is typically subjected to an erase sequence at the end of the manufacturing process. However, since reference cell
22
is isolated from the main memory's program and erase circuitry, it is not erased in this erase sequence and its floating gate is not brought to a neutral position. One method of addressing this problem is to subject the entire memory IC to ultra violet, UV, light for a predetermined period of time at the end of the manufacturing process. Exposure to UV light can erase reference cell
22
, but one cannot be certain that reference cell
22
is fully erased. As a result, sense amplifier
12
must accommodate for such variations, which necessarily slows it down.
As the density of nonvolatile memories continues to increase and their sp
Pathak Jagdish
Pathak Saroj
Payne James E.
Atmel Corporation
Auduong Gene N.
McGuire, Jr. John P.
Nelms David
Schneck Thomas
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