Reference cell circuit for split gate flash memory

Details Reference cell circuit for split gate flash memory Reference cell circuit for split gate flash memory

2001-08-10

2002-05-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S210130

Reexamination Certificate

active

06396740

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a reference cell circuit and more particularly, to a split gate reference cell circuit which may be quickly accessed and which has improved tracking attributes relative to prior reference cell circuits.
BACKGROUND OF THE INVENTION
Semiconductor memory devices typically employ reference cell circuits to access data stored within selected portions of memory by way of one or more bit lines. One type of reference cell circuit implements “split gate flash” type memory cells to access portions of memory. Referring now to
FIG. 1
, there is shown a schematic diagram illustrating a conventional split gate flash type reference cell circuit
10
. Circuit
10
includes a pair of split gate type field effect transistors or flash memory cells
12
,
14
. Cell
12
represents an odd reference cell, and cell
14
represents an even reference cell. Cell
12
includes a control gate
16
which is electrically and communicatively coupled to address bit line XADR[
0
], a floating gate
18
which is electrically coupled to the control gate
16
, a drain
20
and a source
22
. Cell
14
includes a control gate
24
which is electrically and communicatively connected to a conventional logic inverter device
26
. Inverter device
26
is electrically and communicatively coupled to address bit XADR[
0
] and to control gate
24
. Cell
14
further includes a floating gate
28
, which is electrically coupled to the control gate
24
, a drain
30
which is electrically and communicatively coupled to drain
20
, and a source
32
which is electrically and communicatively coupled to source
22
. Based on the control signal received from XADR[
0
], the control and floating gates for the selected cells
12
,
14
are selectively activated and deactivated. Particularly, when the control gate
16
and floating gate
18
are activated for cell
12
, the control gate
24
and floating gate
28
are deactivated for cell
14
, and when the control gate
24
and floating gate
28
are activated for cell
14
, the control gate
16
and floating gate
18
are deactivated for cell
12
. While this reference cell circuit
10
is effective to select between the even cell
12
and odd cell
14
and has acceptable tracking attributes (e.g., tracking of process variation), it suffers from some drawbacks.
Particularly, the floating gates
24
,
28
of the reference cell circuit
10
have relatively high resistance values, and require an undesirable long period of time to for the reference currents to build and for the cells
12
,
14
to reach their respective threshold or “turn-on” voltages. As a result, the access time of the reference circuit
10
is undesirably long (e.g., 200 nanoseconds).
There is therefore a need for a new and improved reference cell circuit or split gate flash memory having a reduced access time relative prior reference cell circuits, while maintaining and/or improving the tracking attributes of the circuit.
SUMMARY OF THE INVENTION
A first non-limiting advantage of the invention is that it provides a reference cell circuit for split gate flash memory which has a reduced access time.
A second non-limiting advantage of the invention is that it provides a method for selecting between split gate type reference cells which has allows for improved tracking of process variation.
According to a first aspect of the present invention, a reference cell circuit is provided for split gate flash memory. The circuit includes a bit line which provides a first signal; an inverter which is coupled to the bit line and which inverts the first signal; a first split gate cell having a first control gate which is electrically coupled to the address line and which receives the first signal, effective to select the first split gate cell when the first signal is high, a first floating gate which is electrically coupled to a constant voltage signal, a first source and a first drain; and a second split gate cell having a second control gate which is electrically coupled to the inverter and which receives the inverted first signal, effective to select the second split gate cell when the first signal is low, a second floating gate which is electrically coupled to the constant voltage signal, a second source, and a second drain.
According to a second aspect of the present invention, a reference cell circuit is provided for split gate flash memory. The circuit includes a bit line which provides a first signal; an inverter which is electrically coupled to the bit line and which inverts the first signal; a first split gate transistor having a first control gate which is electrically coupled to a constant voltage signal, a first floating gate which is electrically coupled to the first control gate and to the constant voltage signal; a second split gate transistor having a second control gate which is electrically coupled to the constant voltage signal, a second floating gate which is electrically coupled to to the second control gate and to the constant voltage signal; a third transistor having a first gate which is coupled to the bit line and which receives the first signal, and a first portion which is coupled to first split gate transistor, effective to select the first split gate transistor when the first signal is high; and a fourth transistor having a fourth gate which is coupled to the inverter and which receives the inverted first signal, and a second portion which is coupled to the second split gate transistor, effective to select the second split gate transistor when the first signal is low.
According to a third aspect of the present invention, a method is provided for selecting between an odd split gate flash memory cell and an even split gate flash memory cell, the odd split gate memory cell including a first control gate and a first floating gate, and the even split gate memory cell comprising a second control gate and a second floating gate, the method comprising the steps of: coupling the first floating gate and the second floating gate to a constant voltage source; communicating a first signal to the first control gate, effective to activate the first control gate when the first signal is high, thereby selecting the odd split gate memory cell, and effective to deactivate the first control gate when the first signal is low, thereby deselecting the odd split gate memory cell; inverting the first signal; and communicating the inverted first signal to the second control gate, effective to deactivate the second control gate when the first signal is high, thereby deselecting the even split gate memory cell, and effective to activate the second control gate when the first signal is low, thereby selecting the even split gate memory cell.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.


REFERENCES:
patent: 5450361 (1995-09-01), Iwahashi et al.
patent: 5684739 (1997-11-01), Takeuchi
patent: 6275419 (2001-08-01), Guterman et al.
patent: 6317362 (2001-11-01), Nomura et al.

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