Reference buffer technique for high speed switched capacitor...

Details Reference buffer technique for high speed switched capacitor... Reference buffer technique for high speed switched capacitor...

2000-04-11

2001-09-04

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S108000, C327S561000, C326S027000

Reexamination Certificate

active

06285231

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of reference buffers. More particularly, the present invention relates to a low power reference buffer including an amplifier with very large transconductance and high frequency non-dominant poles and a triple bonding configuration to a large off-chip capacitor that avoids problems related to the lead wire inductance.
2. Description of the Related Art
Many of the newer analog-to-digital (A/D) converters and other switched capacitor integrated circuits (ICs) have a reference buffer integrated on the chip. This approach increases the chip's functionality, reducing the external component count and the overall system cost.
FIG. 1
illustrates a conventional reference buffer. As shown, a reference buffer A
1
is connected between the reference input V
in
and the internal reference line
101
. Capacitors C
1
and C
2
are parasitic capacitance and switching capacitance on that internal reference line
101
, respectively. More specifically, the switching capacitance C
2
is coupled to the internal reference line
201
by a switch S which is, in turn, controlled by a clock CLK. For conventional high speed, high resolution A/D converter designs, capacitances C
1
and C
2
are on the order of 10 picoFarads (pF) with a switching speed at approximately 40 MHz. Moreover, the settling time within 0.01% (for a 12-bit A/D converter) when the MOS switch S closes is less than ½ clock cycle or about 12 nanoseconds (ns) or less.
Modeling the reference buffer response with a single dominant pole (exponential settling), the required transconductance gm of the reference buffer is determined by the following expression.
g
m
=
2
⁢
π
·
n
·
(
C
1
+
C
2
)
T
s
(
1
)
where T
s
=12 ns is the maximum settling time; (C
1
+C
2
)=20 pF is the total load capacitance; and n is the number of time constant periods for settling, which, in this case, is 10.
In the above numerical example, the required transconductance gm is in excess of 100 mA/V. It should be noted that Equation (1) does not take into account nonlinear effects for settling (slewing) and the loading of the reference line by the output capacitance of the reference buffer itself.
For high speed circuits, the design requirements of the reference buffer are often achieved with a considerable amount of power dissipation. In practice, a reference buffer cannot be designed in a Complementary Metal-Oxide Semiconductor (CMOS) technology with a power budget below 200-300 mW, which is comparable with the rest of the power dissipation in the analog section of the A/D converter.
Some power savings can be achieved in a bipolar, or BiCMOS technology, because of the inherently larger bipolar transconductance for a given bias current. Even with this more expensive technology, however, power dissipation in the reference buffer remains a significant fraction of the overall power consumption.
SUMMARY OF THE INVENTION
In view of the foregoing, the present application discloses a low power reference buffer including an amplifier with very large transconductance and high frequency non-dominant poles and a triple bonding scheme to a large off-chip capacitor that avoids the problems related to the lead wire inductance.
In particular, an apparatus including a reference buffer in accordance with one embodiment of the present invention includes a first amplifier having first and second input terminals and an output terminal, the first amplifier first input terminal configured to receive a first reference signal; a common node; a first inductance coupled between the first amplifier output terminal and the common node; a second inductance coupled between the first amplifier second input terminal and the common node; and a third inductance coupled to the common node; where the first inductance and the second inductance separate the first amplifier output terminal, and the first amplifier second input terminal, respectively, from the common node.
An apparatus including a reference buffer in accordance with another embodiment of the present invention further includes a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; where the second amplifier output terminal and the second amplifier second input terminal are coupled to the third inductance such that the second amplifier output terminal and second amplifier second input terminal are separated from said common node; and further, where the second amplifier first input terminal is configured to receive a second reference signal.
An the voltage gain amplifier of the apparatus including a reference buffer in accordance with yet another embodiment of the present invention includes a first input transistor having first, second and third terminals, the first input transistor first terminal configured to receive a first input signal and the first input transistor second terminal configured to receive a first bias signal; a second input transistor having first, second and third terminals, the first input transistor first terminal configured to receive a second input signal and the second input transistor second terminal configured to receive a second bias signal; and a plurality of diodes coupled to the second terminals of the first and second input transistors; where the second input transistor third terminal is coupled to the first input transistor third terminal, the third terminals further configured to receive a third bias signal.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.


REFERENCES:
patent: 4495472 (1985-01-01), Dwarakanath
patent: 4954769 (1990-09-01), Kalthoff
patent: 5276394 (1994-01-01), Mayfield
patent: 6054886 (2000-04-01), Mayfield
“Adaptive Biasing CMOS Amplifiers”, Marc G. Degrauwe, Jozef Rijmenants, Eric A. Vittoz, IEEE Journal Solid State Circuits (1982).

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