Reference buffer circuits for providing reference voltages

Details Reference buffer circuits for providing reference voltages Reference buffer circuits for providing reference voltages

2011-06-07

2011-06-07

Sterrett, Jeffrey L (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S315000

Reexamination Certificate

active

07956597

ABSTRACT:
A reference buffer circuit provides a reference voltage at an output node and comprises a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising a third MOS transistor. A positive input terminal of the amplifier receives an input voltage. A gate of the first MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to a negative input terminal of the amplifier. A gate of the second MOS transistor is coupled to the drain of the first MOS transistor, a source is coupled to a first voltage source, and a drain is coupled to the source of the first MOS transistor. A gate of the third MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to the output node.

REFERENCES:
patent: 4686451 (1987-08-01), Li et al.
patent: 5422563 (1995-06-01), Pflueger
patent: 5739712 (1998-04-01), Fujii
patent: 7002401 (2006-02-01), Khalid
patent: 2002/0093325 (2002-07-01), Ju
patent: 2007/0090860 (2007-04-01), Hsu
patent: 2007/0241737 (2007-10-01), Yen et al.

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