Reference buffer circuit

Details Reference buffer circuit Reference buffer circuit

2011-04-12

2011-04-12

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S543000

Reexamination Certificate

active

07924087

ABSTRACT:
A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.

REFERENCES:
patent: 5552723 (1996-09-01), Shigehara et al.
patent: 5821769 (1998-10-01), Douseki
patent: 6304110 (2001-10-01), Hirano
patent: 6677803 (2004-01-01), Chiba
patent: 6833749 (2004-12-01), Erstad
patent: 6885234 (2005-04-01), Ando
patent: 7164307 (2007-01-01), Tschanz et al.
patent: 2007/0090860 (2007-04-01), Hsu
patent: 1267406 (2000-09-01), None
English language translation of abstract of CN 1267406 (published Sep. 20, 2000).

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