Special receptacle or package – Holder for a removable electrical component – Bar or tapelike carrier for plural components
Reexamination Certificate
1999-04-30
2001-02-06
Brown, Glenn W. (Department: 2858)
Special receptacle or package
Holder for a removable electrical component
Bar or tapelike carrier for plural components
C206S389000, C206S411000, C226S093000, C414S935000
Reexamination Certificate
active
06182828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bare chip prober device for a bare chip operation test and burn-in test and a bare chip handling method and, in particular, to a device adapted to mount a bare chip on a test board or burn-in board in a bare chip operation testing or burn-in testing and a tape reel with bare chips carried thereon.
2. Description of the Related Art
In the case where a bare chip with, for example, solder or gold bumps formed thereon is to be mounted on a substrate in a flip-chip fashion, it is necessary to use a bare chip whose operation reliability is ensured. In order to prove the reliability, a burn-in test is carried out.
At the burn-in test, unlike a semiconductor device mounted in a package, the bare chip cannot be mounted directly on a burn-in board. As shown in
FIG. 7A
, the bare chip
1
is mounted on a carrier
22
and the carrier
22
is held in place in a socket above the burn-in board. In this way, the reliability test is carried out.
FIGS. 8A
to
8
C show the conventional method for mounting the bare chip
1
on the carrier.
Bump electrodes
25
are formed on the chip
1
and formed of, for example, a high-melting-point 90-Pb/10 Sn solder. An electrode
26
is provided on the carrier
22
and an eutectic solder
27
is provided on the electrode
26
. The bare chip
1
is placed on the carrier
22
in a manner to set the bump electrode
25
in contact with the eutectic solder
27
above the electrode
26
. Then, the eutectic solder
27
is melted to allow the bump electrode
25
to be soldered to the electrode
26
.
In the method for mounting the bare chip
1
on the carrier
22
by soldering, after the test has been done, it is necessary to separate the chip
1
away from the carrier
22
so that the chip
1
may be actually mounted on a substrate. For this reason, there is a high possibility that damage will be caused to the bump electrode
25
and chip
1
. This method can be applied to the bump electrode using a high-melting-point solder, but it cannot be used for an eutectic solder and gold bump electrodes, thus presenting a problem.
FIG. 9
shows another method for mounting the bare chip on the carrier.
Solder bump electrodes
8
are provided on the chip
1
. First, the chip
1
is located in an interposer
29
which is, in turn, located on the carrier
22
. Thereafter, a cover
21
with rubber
20
attached to its lower surface is placed over the carrier
22
with the interposer
29
and chip
1
in between and is fixed to the carrier
22
by a fastening means
28
. As a result, the chip
1
is held in the carrier
22
with the interposer
29
in between.
This method poses the problem with the chip-to-carrier alignment as well as the manufacturing accuracy of the chip and carrier. The greater the number of the bumps
8
, the more difficult it is to achieve adequate accuracy so that all the bumps on the chip
1
are contacted with the corresponding electrodes of the carrier
22
.
Bare chips
1
are conveyed to a chip tray
19
as shown in
FIG. 7B
, before and after the test, in a manner to be carried on the chip tray
19
.
In the case where the chips
1
, being carried on the chip tray
19
, is handled, it takes a lot of time to place the bare chips onto the chip tray
19
or it is necessary to wash the chip tray
19
or to use a different chip tray if the size of the chips
1
is different, thus preventing the problem of preparing more chip trays of different sizes.
In the case where the carrier is used, it has to be manually handled in a bare chip operation confirmation test to be done before and after the burn-in process, thus lowering the test efficiency.
BRIEF SUMMARY OF THE INVENTION
It is accordingly an aspect of the present invention to provide a high-throughput reliability evaluation system involving less damage to chips, which can be achieved with the use of a chip mounting device having an aligning mechanism and a test board for the chip mounting device and a chip conveying tape.
This aspect of the present invention can be achieved by the following arrangement.
A bare chip prober apparatus includes:
a first pickup mechanism for picking up a semiconductor bare chip having an initial orientation from a reel tape with a plurality of semiconductor bare chips carried thereon and for setting a bare chip in a substantially inverted orientation;
an aligning/mounting mechanism for aligning the picked-up semiconductor bare chip with a board for testing and for detaching the semiconductor bare chip from the board after the test has been finished; and
a second pickup mechanism for setting the detached semiconductor bare chip onto the reel tape.
Another aspect of the invention includes a reed tape having:
a chip mounting section adapted to allow a bare chip to be bonded thereto and mounted in place thereon;
a protection member provided along a tape conveying direction and adapted to prevent contacting between the chip and the tape when the tape is wound; and
a tape bending area provided at a forward end and back end of, and near, the chip mounting section in the tape conveying direction and providing a bendable thin-walled area.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4818726 (1989-04-01), Flaten
patent: 4956605 (1990-09-01), Bickford et al.
patent: 5076427 (1991-12-01), Thomson et al.
patent: 5189363 (1993-02-01), Bregman et al.
patent: 5232532 (1993-08-01), Hori
patent: 5318181 (1994-06-01), Stover et al.
patent: 5510724 (1996-04-01), Itoyama et al.
patent: 5561386 (1996-10-01), Funaki et al.
patent: 5578919 (1996-11-01), Semba et al.
patent: 5614837 (1997-03-01), Itoyama et al.
patent: 5931337 (1999-08-01), Ando et al.
Brown Glenn W.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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