Reed-Solomon code system employing k-bit serial techniques for e

Details Reed-Solomon code system employing k-bit serial techniques for e Reed-Solomon code system employing k-bit serial techniques for e

1993-05-03

1997-08-19

Baker, Stephen M.

Excavating

371 381, 371 391, 371 4011, G11B 2018, H03M 1300, H03M 1322

Patent

active

056595573

ABSTRACT:
Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

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