Redundary circuit with a spare main decoder responsive to an add

Details Redundary circuit with a spare main decoder responsive to an add Redundary circuit with a spare main decoder responsive to an add

1987-11-30

1989-06-06

Hecker, Stuart N.

Excavating

36523003, 36518905, 365210, 365200, 36523006, G11C 700, G11C 2900, G11C 800

Patent

active

048377473

ABSTRACT:
A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals "0". The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals "1". A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

REFERENCES:
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patent: 4547867 (1985-10-01), Reese et al.
patent: 4556975 (1985-12-01), Smith et al.
patent: 4601019 (1986-07-01), Shah et al.
patent: 4639895 (1987-01-01), Iwahashi et al.
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4727516 (1988-02-01), Yoshida et al.
ISSCC 83, Feb. 23, 83, CMOS Memory, Digest of Technical Papers "A 64kbf.CMOS RAM with Divided WL Structure", by Yoshimoto et al., pp. 58-59.
Electronics, Posa, John G.: "Redundancy", Jul. 28, 1981, pp. 116-134.
IEEE Journal of Solid-State Circuits, Robert T. Smith et al., "Laser Programmable Redundancy and Yield, Improvement in a 64K DRAM", vol. SC-16, No. 5, Oct. 1981.
IEEE Journal of Solid State Circuits, Kim C. Hardee et al., "A Fault-Tolerant 30 ns/375 mW 16K x 1 NMOS Static Ram."

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