Redundant storage device having address determined by parity of

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G06F 1110

Patent

active

047747129

ABSTRACT:
A memory device for storing data and providing address and data line error detection is disclosed. A memory holds two copies of data, each copy of data having opposite parity dependent on its address. An address sequencer provides addresses to the memory. The addresses are modified to select the copy of data in the memory having a predetermined first parity. A parity checker checks the parity of data provided by the memory and provides an error indication if the parity is incorrect, said error indication being indicative of address and data line errors and memory cell errors. When an error is indicated by an error latch, the error causes a retry of the memory in the location where the desired data is stored with parity opposite the first parity.

REFERENCES:
patent: 4271521 (1981-06-01), Mahmood
patent: 4346474 (1982-08-01), Sze
patent: 4404647 (1983-09-01), Jones et al.
patent: 4464747 (1984-08-01), Groudon
patent: 4464754 (1984-08-01), Stewart

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