Redundant source synchronous busses

Multiplex communications – Fault recovery – Bypass an inoperative switch or inoperative element of a...

Reexamination Certificate

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Details

C370S228000, C710S120000

Reexamination Certificate

active

06646982

ABSTRACT:

The invention relates generally to electrical circuits, and more particularly to communication busses and switching circuits.
BACKGROUND
A communications bus can be used to couple plural electrical circuit elements. Optimally, the communications bus should be transparent to the devices that it interconnects. A source synchronous communications bus can be used to couple a source device to one or more receiving devices. In a source synchronous communications link, the source device provides a sourcing clock signal that can be used by a receiving device to synchronize the reading of data from the communications link.
Electrical designs for mission critical systems must provide reliability. Redundancy can be built into a mission critical system to provide a measure of reliability. For example, a system designer may provide a design that includes a master system that is supported by a fully redundant slave system. In the event a failure arises in the master system, the slave system can be utilized to support system requirements. However, the transition from the master system to the slave system can cause problems. Depending on the system design requirements, the slave system may be required to take over immediately so that no down time is experienced. Alternatively, the master system may need to be taken off line prior to the starting of the slave system. Information may be required to be shared between the master and slave system in order to support the transition. Timing and control issues and glitches are some of the problems that must be resolved when introducing redundancy to a system.
SUMMARY
In one aspect, the invention provides a redundant source synchronous communications bus coupling a first component and a second component. The first component includes a clock source and one or more data channels where each data channel includes a transmitter. The second component includes redundant termination systems for receiving signals generated in each data channel. The redundant source synchronous communications bus includes a plurality of first, second and third transmission line portions. Each first transmission line portion is coupled to a transmitter in the first component. The bus further includes a like plurality of transistor switches. Each transistor switch includes an input port, two output ports and primary and redundant switches operable for switching a signal received from the first transmission line portion at the input port to either of the two output ports. Each output port is coupled by the second and third transmission line portions, respectively, to the redundant termination systems in the second component.
Aspects of the invention can include one or more of the following features. The redundant source synchronous bus can include a like plurality of bias circuits. Each bias circuit can be coupled between an output of a transmitter for a data channel and ground. The redundant source synchronous bus can include a like plurality of AC coupling capacitors. Each AC coupling capacitor can couple the output of a transmitter for a data channel to one end of a first transmission line portion, where the second end of the first transmission line portion is coupled to the input port of a transistor switch. A length of each first transmission line portion can vary while an overall length between the first and second component is approximately equal for all data channels.
In another aspect, the invention provides a system for coupling a first component and a second component. The first component includes plural redundant source synchronous communication links. Each link includes a clock source and one or more data channels where each data channel includes a transmitter. The second component includes plural redundant termination systems for receiving signals generated in each data channel. The system includes means for staggering signals generated on each source synchronous communication bus so that no two of the plural source synchronous communications busses are sourcing signals at a same time.


REFERENCES:
patent: 5843799 (1998-12-01), Hsu et al.
patent: 6393504 (2002-05-01), Leung et al.
patent: 6400771 (2002-06-01), Humphrey
patent: 6433600 (2002-08-01), Ilkbahar
patent: 6483755 (2002-11-01), Leung et al.
patent: 6510503 (2003-01-01), Gillingham et al.

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