Redundant signed digit A-to-D conversion circuit and method ther

Details Redundant signed digit A-to-D conversion circuit and method ther Redundant signed digit A-to-D conversion circuit and method ther

1995-06-05

1997-07-01

Gaffin, Jeffrey A.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341161, 341162, H03M 140

Patent

active

056443137

ABSTRACT:
RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.

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"A 12 Bit 600kS/s Digitally Self-calibrated Pipeline Algorithmic ADC," by H. Lee, published in Dept. of EECS, Massachusetts Institute of Technology, pp. 121-122. (no date given).
"A CMOS 13-b Cyclic RSD A/D Converter," by B. Ginetti et al., published in the IEEE Journal of Solid-State Circuits, vol. 27, No. 7, Jul. 1992, pp. 957-965.

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