Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2003-03-04
2004-08-17
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S786000, C361S723000, C361S772000, C361S813000
Reexamination Certificate
active
06777790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices in general and, more particularly, to redundant pinout package configurations for connecting the semiconductor device to a host electronic apparatus or substrate.
2. State of the Art
Modern packaged integrated circuits (IC) comprise one or more encapsulated semiconductor devices or chips within a protective “package” of plastic, ceramic, other moldable material, or hermetically sealed package. Typically, a large number of semiconductor devices are formed from a wafer made from a semiconductor material such as silicon, germanium or gallium arsenide. Microscopic circuits are formed on a surface of each semiconductor device by photolithographic techniques and are typically attached to a lead frame with conductive wires. More particularly, a plurality of leads of the lead frame is connected to bond pads on the semiconductor device or semiconductor dice, enabling the dice to be electrically interconnected to an external electrical apparatus.
On first generation IC devices, the semiconductor devices were relatively large, consuming most of the package space. The number of leads attached to the semiconductor device was also very limited. Thus, wide, short leads located adjacent the bond pads of the semiconductor device were used. The resulting wire bonds were short, and the inductance between the semiconductor device and the host apparatus was low.
In later generation IC devices, the semiconductor devices have become progressively smaller while the numbers of leads have typically increased. As a result, the lead frame leads of such semiconductor devices must, out of necessity, be much narrower and much longer, both of which increase the lead inductance and slow the speed of the device. In addition, the high density of wire connections typically makes wire bonding more difficult and results in an increase in bond failures. Furthermore, with very small semiconductor devices, the very fine wires connecting the semiconductor device to the leads of the lead frame may be very long, resulting in “wire sweep,” sagging, short circuiting, and bond failure during encapsulation.
High inductance and reduced speed limit the usefulness of the packaged semiconductor device while shorting or destruction of the wire bonds will make the semiconductor device useless.
In the conventional package having a semiconductor device attached to a paddle, a reduction in device size and increase in bond pad density have also resulted in the die paddle support arms being longer, narrower, and weaker. Thus, problems in supporting the semiconductor device during attachment and wire bonding have increased.
The required spacing, width, and length of leads and wires have become a serious limitation in the further size reduction of semiconductor devices. While complex integrated circuits may be formed in very small semiconductor devices, connecting such a device or devices to a host apparatus while maintaining the semiconductor device characterization may be very difficult.
There have been various attempts at overcoming the high inductance or interactive conductance effects of small semiconductor devices. For example, in U.S. Pat. No. 5,521,426 to Russell, a leads-over-chip (LOC) semiconductor device with long, narrow leads is disclosed. In order to decrease the capacitance between the leads and the semiconductor device and increase lead strength, the leads are stamped or rolled to have a non-rectangular cross-section, such as a “U” configuration. Thus, the strength of the lead and its cross-sectional area are increased, resulting in less lead sag and reduced capacitative interaction. However, the cost of producing such leads is considerable, and the package thickness is increased. Furthermore, the method does not increase the size of wire bonding areas on the lead fingers of the lead frame, and the wire bonding operation is no easier.
While custom and semi-custom semiconductor devices are widely used in the electronics industry, a large part of the semiconductor device market is filled by semiconductor devices which may be used in a variety of applications, by using less than the maximum number of functions provided by the circuits thereon. Such a versatile semiconductor device may generally be made more cheaply than each of the custom semiconductor devices which it replaces. The current practice in the semiconductor industry is to produce semiconductor devices which have a generally wide versatility, i.e. they may be connected in different apparatus for performing a variety of electronic functions.
In a semiconductor device, more than one bond pad may be connected to a single exterior lead of a lead frame, or more than one exterior lead may be connected to a single bond pad. In many cases, however, each bond pad is connected to a single exterior lead of a lead frame.
The particular lead finger of a lead frame with which a bond pad is connected determines the “pinout” for that bond pad for the packaged semiconductor device. For example, in a dynamic random access memory (DRAM), if a bond pad on the semiconductor device which corresponds to Address
0
(AO) is bonded to the lead finger of a lead frame corresponding to Output Pin
5
, then pin
5
on the package is used as AO. This hard wires the bond pad on the semiconductor device to the output of the lead frame, and remains that way for the life of the packaged semiconductor device.
U.S. Pat. No. 5,360,992 of Lowrey et al. proposes a two-part or three-part semiconductor package by which a semiconductor device circuit may be adapted to a variety of host apparatus following encapsulation of the device. Various “lead frames” of differing configurations are alternatively joined or attached to the encapsulated semiconductor device to provide the required pinout pattern. This method does nothing to reduce lead length (lengths may be increased) or increase the lead width.
In U.S. Pat. No. 5,256,598 of Farnworth et al., the concept of using a single “generic” lead frame for semiconductor devices of various sizes, cutting a device placement hole in the lead frame to match a particular device size, is illustrated. The number of lead fingers is fixed, and must be the maximum usable with the variety of semiconductor devices to be accommodated. As the semiconductor device size is decreased, the lead lengths must, out of necessity, be increased and their widths decreased, so the problem of high inductance is not solved.
It has been proposed to build functional redundancy into semiconductor devices, whereby extra circuit components are included to be used if one or more components are defective or inoperable. A larger semiconductor device must be used to accommodate the extra components as well as the extra circuitry for detecting functioning
on-functioning components and direct the selection of a functioning component. In addition, it may be necessary to provide means, such as a fuse, to internally disconnect unused circuitry. While such redundancy in electronic devices may be very useful at the design and development stages, it is of limited use in large scale production.
Whether the semiconductor device is configured to have a “generic” register for adaptation to many applications, or has functional redundancy, or both, in nearly all cases there are “No Connects” (NC) and/or missing pins identified in the registration. “No Connect” leads are typically found in a central portion of the lead frame, where bonding wires are usually short. Examples of such are the 20/26L SOJ (small outline J-bend) and 44/50L TSOP II (thin small outline package) devices.
SUMMARY OF THE INVENTION
The present invention is directed to a configuration for a semiconductor device where the package pinout registration has redundancy for critical signals to provide low inductance and high yield for all generations of the packaged semiconductor device.
The invention comprises the configuration of a semiconductor device wherein central lead locations normally identified in the register as “No Connects” (
Chambliss Alonzo
Micro)n Technology, Inc.
TraskBritt
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