Redundant micro-loop structure for use in an integrated...

Details Redundant micro-loop structure for use in an integrated... Redundant micro-loop structure for use in an integrated...

2011-06-14

2011-06-14

Sandvik, Benjamin P (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257SE23141

Reexamination Certificate

active

07960836

ABSTRACT:
An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

REFERENCES:
patent: 2003/0067075 (2003-04-01), Fukasawa
Bickford et al.; Yield Improvement by Local Wiring Redundancy; IEEE Computer Society, Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED '06), 0-7695-2523-7/06; 6 pages.

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