Redundant encryption processor arrangement for use in an electro

Details Redundant encryption processor arrangement for use in an electro Redundant encryption processor arrangement for use in an electro

1988-12-09

1991-06-04

Cangialosi, Salvatore

Cryptography

Equipment test or malfunction indication

380 49, 364200, H04L 900

Patent

active

050220764

ABSTRACT:
An improved fault tolerant processor arrangement is described. In accordance with this invention, redundant processors are coupled in parallel in a master/slave configuration wherein means are provided for disabling the respective outputs of the processors. The master processor includes means for generating a periodic pulse which is detected by the slave processor. As long as the periodic pulse is detected by the slave processor, the output of the master processor remains enabled and the output of the slave processor is disabled. If the periodic pulse is not detected by the slave processor, the slave processor disables the output of the master processor wherein the output of the slave processor becomes enabled.

REFERENCES:
patent: 4015246 (1977-03-01), Hopkins, Jr. et al.
patent: 4392199 (1983-07-01), Schmitter et al.
patent: 4453215 (1984-06-01), Reid
patent: 4493028 (1985-01-01), Heath
patent: 4654819 (1987-03-01), Stiffler et al.

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