Redundant clock signal generating circuitry

Details Redundant clock signal generating circuitry Redundant clock signal generating circuitry

1979-07-02

1981-08-04

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

307219, 331 49, 331 55, 331 56, 331DIG2, H03L 700

Patent

active

042824931

ABSTRACT:
A clock signal generator for providing redundant clock signals includes two clock modules that utilize phase-locked loop oscillators for generating clock and reference signals and for diagnosing malfunctions of the generated clock and reference signals. One clock module is selected as the master, and the other clock module is the slave, being phase and frequency locked to the master. Switching the master between the clock modules may be externally initiated by select signals and also is automatically initiated when malfunctions are detected. The master and slave clock modules are always phase and frequency locked to one another, even if both clock modules are malfunctioning. When both clock modules experience simultaneous malfunctions, the master is selected in accordance with the externally generated select signals. Since the master and slave clock modules are always phase and frequency locked, switching the master is transparent to clock signal utilization circuitry. The redundant clock signal generator may be advantageously utilized in time-division-multiplex communication systems where uninterruped clock signals are necessary for signal transmission and reception.

REFERENCES:
patent: 3769607 (1973-10-01), Thelen
patent: 3795872 (1974-03-01), Napolitano et al.
patent: 4025874 (1977-05-01), Abbey

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