Redundant bubble memory control system

Details Redundant bubble memory control system Redundant bubble memory control system

1978-04-19

1980-11-11

Moffitt, James W.

Static information storage and retrieval

Magnetic bubbles

Plural interacting paths

365 1, G11C 1908

Patent

active

042336694

ABSTRACT:
A memory control system comprises a memory unit including a plurality of chips each having a shift register type memory having a plurality of information loops, the number of chips being larger than a predetermined number, the predetermined number of bits out of those bits which are read from or written into the information loops of the respective chips at the same timing constituting a unit information; and an additional memory which stores information indicative of normal loop condition or defective loop condition for each of the information loops in each of the chips and information indicative of whether the number of normal loops in each information loop group corresponding to the bits which are read or written at the same timing is larger than said predetermined number or not. Based on the information stored in said additional memory, only the predetermined number of normal loops are selected from the information loops corresponding to the bits which are read or written at the same timing, and when the number of normal loops does not reach the predetermined number, the information loops at that timing are not used.

REFERENCES:
patent: 4073012 (1978-02-01), Ohnigian
IBM Technical Disclosure Bulletin-vol. 19, No. 12, May 1977, pp. 4758-4761.
IEEE Transactions on Magnetics-vol. mag-10, Sep. 1974, pp. 852-855.

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