Redundancy structure in self-aligned contact process

Details Redundancy structure in self-aligned contact process Redundancy structure in self-aligned contact process

1999-06-10

2001-11-20

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to nonconductive state

C438S006000, C438S281000, C438S601000

Reexamination Certificate

active

06319758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits and electronic devices formed on a semiconductor substrate. Particularly, this invention relates to fuse link structures and methods of fabrication of fuse link structures that selectively implement redundant circuits with the integrated circuits.
2. Description of the Related Art
Often complex integrated circuits are formed on semiconductor substrates having redundant functional circuits. These redundant functional circuits are implemented to insure improved yields in the manufacture of the integrated circuits. To eliminate malfunctioning circuits and to substitute functioning redundant circuits for the malfunctioning circuits, fuse links are placed appropriately within the integrated circuits. An example of this is in memory integrated circuits such as dynamic random assess memory (DRAM) and static random access memory (SRAM). The memory array is formed with redundant rows and columns of memory cells connected to the row and column address decoders. Prior to final assembly of the memory integrated circuit into a functioning package, each integrated circuit chip or memory chip is tested for functionality. Those columns and rows of the memory array having nonfunctioning memory cells are eliminated from the memory array and the redundant memory rows and columns are implemented within the array to replace the malfunctioning columns and rows.
To perform the removal of the malfunctioning circuits and to implement the redundant circuit, destructible fuse links are formed at appropriate connective locations between operating functions of the integrated circuits, the redundant circuit functions, and the malfunctioning circuits. The fuse links are selectively destroyed to open the connection of the fuse link.
Conventionally, the fuse link is a layer conductive material such as a metal, a heavily doped polycrystalline silicon, or a layer of heavily doped polycrystalline silicon covered with a layer of a metal alloyed with the heavily doped polycrystalline silicon. The layer of conductive material is covered with a transparent insulative layer to protect the conductive material from contamination from the external environment.
If the fuse is to be destroyed, the fuse is subjected to excessive current or to an intensive laser light to sufficiently heat the layer of conductive material to destroy it. Currently, the conventional method of destruction is the use of an intense laser light. This requires the covering insulative layer be sufficiently transparent and sufficiently thin to allow the laser light to penetrate directly to the layer of conductive material.
U.S. Pat. No. 5,729,041 (Yoo et al.) describes a structure and method of forming a fuse and fuse window having a protective layer formed over them. The protective layer is highly transmissive to intense laser light while it is protective of the fuse and the surrounding insulating layers.
U.S. Pat. No. 4,6517409 (Ellsworth et al.) describes a fuse programmable read only memory (PROM). The fuse programmable PROM has a merged vertical fuse/bipolar transistor.
U.S. Pat. No. 5,754,089 (Chen et al.) describes a fuse structure in which a metallic frame is inserted between the interlayer dielectric insulation layers. The metallic frame is used as a mask to form the fuse window to simplify alignment and to minimize problems due to insulation residue on the surface of the fuse window layer.
U.S. Pat. No. 5,567,643 (Lee et al.) describes a method for creating a guard ring around a fuse link. The guard ring prevents contaminants from diffusing through a window opening above a fuse link to adjacent semiconductor devises. The guard ring is an annular metal ring that penetrates two or more insulating layers and contacts to the semiconductor substrate.
SUMMARY OF THE INVENTION
An object of this invention is to form a fuse link to implement redundant circuits within an integrated circuit.
Another object of this invention is to create a fuse link where an insulating layer over a conductive layer of the fuse link is sufficiently thin and sufficiently transparent to allow destruction of the conductive layer by an intense laser light.
To accomplish these and other objects, a redundancy structure for implementation of redundant circuits within an integrated circuit placed on a semiconductor substrate includes a fusible link. The fusible link is formed of a layer of a conductive material deposited upon an insulating layer of the semiconductor substrate connected between the redundant circuits and other circuits present on the integrated circuit. The insulating layer is generally a layer of field oxide placed on the surface of the semiconductor substrate. The layer of conductive material is either formed of a metal such as Aluminum (Al) or Tungsten (W), a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten (W) and a heavily doped polycrystalline silicon.
A hard mask layer is placed upon the layer of conductive material during transistor processing to protect the layer of conductive material during formation of self-aligned sources and drains of transistors of the integrated circuit. The hard mask layer is removed from the layer of conductive material for deposition of interlayer dielectric layers on the semiconductor substrate to improve a fuse destruction to implement the redundant circuits.
An opening is formed in the interlayer dielectric layers to thin the interlayer dielectric layers to allow exposure of the layer of conductive material to facilitate destruction of the layer of conductive material.
The redundancy structure of this invention allows the redundant columns or rows of a DRAM array to be implemented and connected to the row address and column address decoders of the DRAM array to improve the yield of the DRAM array.
The hard mask layer is generally a single layer of silicon nitride or two layers composed of silicon dioxide and the second layer is silicon nitride. If the hard mask layer is a single layer of silicon nitride, it has of from approximately 1500 Å to approximately 3000 Å. However, if the hard mask layer is the two layer, the first layer of silicon dioxide has a thickness of from approximately 100 Å to approximately 1000 Å and the second layer of silicon nitride has a thickness of from approximately 1000 Å to approximately 3000 Å.
The opening in the interlayer dielectric above the layer of conductive material has a bottom portion that extends to between approximately 4000 Å and approximately 10,000 Å above the layer of conductive material. The interlayer dielectric is a layering of an undoped oxide and a borophososilicate glass and is formed such that the bottom portion of the opening in the interlayer dielectric has sufficient transparency to allow destruction of the layer of conductive material.
The hard mask layer is too thick and is thus removed to allow destruction of the layer of conductive material.


REFERENCES:
patent: 4628590 (1986-12-01), Udo et al.
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 5041897 (1991-08-01), Machida et al.
patent: 5235205 (1993-08-01), Lippitt
patent: 5567643 (1996-10-01), Lee et al.
patent: 5729041 (1998-03-01), Yoo et al.
patent: 5754089 (1998-05-01), Chen et al.
patent: 5970346 (1999-10-01), Liaw

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