Redundancy scheme for a memory integrated circuit

Details Redundancy scheme for a memory integrated circuit Redundancy scheme for a memory integrated circuit

2006-12-26

2006-12-26

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S229000, C365S200000

Reexamination Certificate

active

07154803

ABSTRACT:
A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line. A memory sector unusable status indicator element is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.

REFERENCES:
patent: 5262993 (1993-11-01), Horiguchi et al.
patent: 5428621 (1995-06-01), Mehrotra et al.
patent: 5659550 (1997-08-01), Mehrotra et al.
patent: 5768196 (1998-06-01), Bloker et al.
patent: 5822256 (1998-10-01), Bauer et al.
patent: 6058052 (2000-05-01), Steadman
patent: 6075729 (2000-06-01), Ohhata et al.
patent: 6078540 (2000-06-01), Keeth
patent: 6141267 (2000-10-01), Kirihata et al.
patent: 6233181 (2001-05-01), Hidaka
patent: 6313695 (2001-11-01), Ooishi et al.
patent: 6535437 (2003-03-01), Silver et al.
patent: 6865133 (2005-03-01), Tsukidate et al.
patent: 6873555 (2005-03-01), Hiraki et al.
patent: 6947329 (2005-09-01), Campardo et al.
patent: 0 626 645 (1994-11-01), None
patent: WO 90/12401 (1990-10-01), None

Affiliated with

Also associated with

Rating

Redundancy scheme for a memory integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundancy scheme for a memory integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy scheme for a memory integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3665753