Redundancy method and structure for 2-bit non-volatile memory ce

Details Redundancy method and structure for 2-bit non-volatile memory ce Redundancy method and structure for 2-bit non-volatile memory ce

1999-02-04

2000-11-14

Elms, Richard

Static information storage and retrieval

Floating gate

Particular connection

36518503, 365200, G11C 1606

Patent

active

061479047

ABSTRACT:
A redundancy method and structure for 2-bit non-volatile memory cells formed in a memory array. The 2-bit memory transistors are arranged to form bit locations, each bit location including eight charge trapping regions. An initial charge trapping region is addressed during program (write) and read operations directed to the bit location, with seven redundant charge trapping regions being maintained in an erased state. At a predefined time, such as when operation of the initial charge trapping region declines due to repeated use, one of the redundant charge trapping regions replaces the initial charge trapping region, and is addressed during program (write) and read operations directed to the bit location. Redundancy data is stored in a supplemental non-volatile memory location of the memory array. The redundancy data identifies a currently-used charge trapping region of a bit location, and instructs addressing circuitry to store bit data addressed to that bit location in the currently-used charge trapping region. After a charge trapping region performance is used (i.e., when performance declines), the redundancy data is updated such that bit data addressed to the bit location is stored in another (redundant) charge trapping region assigned to the bit location.

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patent: 5898197 (1999-04-01), Fujiwara
patent: 5905673 (1999-05-01), Khan
patent: 5909390 (1999-06-01), Harari

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