Redundancy method and a device for a non-volatile semiconductor

Details Redundancy method and a device for a non-volatile semiconductor Redundancy method and a device for a non-volatile semiconductor

1999-03-25

2000-10-17

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

365200, G11C 1606

Patent

active

061341428

ABSTRACT:
In a non-volatile semiconductor memory composed of floating gate field effect transistors arranged in rows and columns forming an array, a redundancy method is provided which includes the steps of: providing one or more column lines for redundancy, in which floating gate FETs in a number as many as the row lines of the array are connected; when a defect occurs in a column line, setting the thresholds of at least all the floating gate FETs connected to the defective column line, to the high state; and using as the substitute memory, the floating gate FETs for redundancy connected to redundancy column lines in a number as many as those of the floating gate FETs of which the thresholds are set in the high state.

REFERENCES:
patent: 5526307 (1996-06-01), Yiu et al.
Hirano et al. (1997-05). "A Sesing Scheme for a ACT flash memory,"Technical Report of the Institute of Electronics Information and Communication Engineers, ICD 97-21,pp. 37-42. English Abstract Only.
Nozoe. (1995-05). "32 Mb and Flash Memory,"Technical Report of the Institute of Electronics Information and Communication Engineers, ICD 95-39, pp. 63-68. English Abstract Only.
Tsao et al. (Jun. 8-10, 1995). "A 5V-only 16M Flash Memory Using A Contactless Array of Source-Side Injection Cells,"1995 Symposium on VLSI Circuits: Digest of Technical Papers 10-2,pp. 77-78.
Yamauchi et al. (Dec. 10-13, 1995). "A New Cell Structure for Sub-Quarter Micron High Density Flash Memory,"International Electron Devices Meeting Technical Digest 95, pp. 267-270.

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