Redundancy in column parallel or row architectures

Details Redundancy in column parallel or row architectures Redundancy in column parallel or row architectures

2004-08-20

2009-06-30

Tran, Nhan T (Department: 2622)

Television

Camera, system and detail

Solid-state image sensor

C348S319000, C348S241000, C348S246000, C257S291000, C250S208100

Reexamination Certificate

active

07554589

ABSTRACT:
A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row circuits. Each column or row circuit include circuitry for controllably coupling the column or row circuit to one of plural signal lines from an array of pixels. A control mechanism is used to select a configuration of plural column or row circuits in the column or row circuitry. In this manner, some column or row circuits are decoupled from the pixel in favor of other column or row circuits. The decoupled column or row circuits may include defective or noisy circuits.

REFERENCES:
patent: 6803782 (2004-10-01), Koob et al.
patent: 6928535 (2005-08-01), Yamashita et al.
patent: 7002628 (2006-02-01), Panicacci
patent: 7023031 (2006-04-01), Tsai
patent: 2002/0001896 (2002-01-01), Yoon
patent: 2002/0017666 (2002-02-01), Ishii et al.
patent: 2003/0076431 (2003-04-01), Krymski
patent: 2003/0146991 (2003-08-01), Barna et al.
patent: 2004/0239789 (2004-12-01), Bruce et al.
patent: 2006/0125940 (2006-06-01), Tinkler et al.

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