Redundancy enable/disable circuit

Details Redundancy enable/disable circuit Redundancy enable/disable circuit

1986-09-18

1987-08-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307441, 307449, 307451, 307469, 307219, 365200, H03K 19003, H03K 19094

Patent

active

046894942

ABSTRACT:
A redundancy enable/disable circuit for enabling and disabling subsequently the use of redundant elements includes first through third P-channel MOS transistors, an N-channel MOS transistor, an enable fuse, and a disable fuse. The enable fuse is blown so as to enable the use of the redundant elements, and the disable fuse is blown subsequently to disable use of the redundant elements.

REFERENCES:
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4476546 (1984-10-01), Varshney
patent: 4592025 (1986-05-01), Takemae et al.
patent: 4613959 (1986-09-01), Jiang
patent: 4614881 (1986-09-01), Yoshida et al.
patent: 4621346 (1986-11-01), McAdams
patent: 4639895 (1987-01-01), Iwahashi et al.
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4651030 (1987-03-01), Mimoto
Taylor et al, "A 1-Mbit CMOS DRAM with a Divided Bitline Matrix Architecture", IEEE JSSC, vol. SC-20, No. 5, Oct. 1985, pp. 894-902.
Fitzgerald et al, "Semiconductor Memory Redundancy at the Module Level", IBM T.D.B., vol. 23, No. 8, Jan. 1981, pp. 3601-3602.
Abbott et al, "Equipping a Line of Memories with Spare Cells", Electronics, Jul. 1981, pp. 127-130.

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