Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-08-02
2003-07-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090, C365S185330, C365S200000
Reexamination Certificate
active
06594177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a redundancy technique for nonvolatile memory devices, and particularly to a circuit and method for replacing defective memory cells in a nonvolatile memory device based upon the type of defect.
2. Description of the Related Art
The first nonvolatile memories were electrically programmable read-only memories (EPROMs). In these memories, the memory cells include a floating-gate transistor that is programmable using the hot carrier effect. Programming of an EPROM memory cell includes applying a potential difference between the drain and the source of the floating gate transistor in the presence of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (hence the term “hot carriers”). The high difference in potential between the control gate and the source of the floating gate transistor gives rise to a strong electrical field between the floating gate and the substrate, the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a “programmed” state.
The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a relatively small silicon area and the effectuation of large scale integration. By contrast, the erasure of all the memory cells of the memory is done substantially simultaneously by exposing the memory cells to ultraviolet radiation.
In addressing the need to individually erase EPROM memory cells, electrically erasable programmable read only memories (EEPROMs) were created. These memories are electrically programmable and erasable by tunnel effect (i.e., the Fowler Nordheim effect). The memory cells have a floating-gate transistor whose drain is connected to the bit line by a selection transistor. The gate of the selection transistor is connected to the word line. The gate of the floating-gate transistor is controlled by a bias transistor. Generally, the source of the floating gate transistor is connected to a reference potential, such as ground. These floating-gate transistors have an oxide layer between the substrate and the floating gate that is very thin to enable the transfer of charges by tunnel effect. The advantage of EPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other EEPROM cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration is achieved.
A third type of memory has more recently gained popularity. This type of memory, flash EPROMS, combines the relatively high integration of EPROMs with the ease of programming and erasure of EEPROMs. Flash memory cells can be individually programmed utilizing the hot carrier effect in the same way as EPROM cells are programmed. Flash memory cells are also electrically erasable by the tunnel effect. The memory cells of a flash EPROM memory includes a floating-gate transistor that has an oxide layer whose thickness is greater than the oxide layer thickness of an EEPROM floating gate transistor but smaller than the oxide layer thickness of an EPROM floating gate transistor. Consequently, the flash memory cell is capable of erasure by the tunnel effect. For erasure, a highly negative potential difference is created between the control gate and the source of the floating gate transistor, the drain being left in the high impedance state or connected to the ground potential so that a high electrical field is created which tends to remove the electrons from the floating gate.
Referring to
FIG. 1
, flash EPROM devices, hereinafter referred to as flash memory devices, typically include at least one array A of flash memory cells organized into rows and columns of flash memory cells. Array A is typically partitioned into blocks B, each of which is further divided into sectors S. Each column of memory cells is coupled to a distinct local column line. Array A typically includes a plurality of main column lines. A plurality of local column lines are selectively connected to each main column line. Each local column line is connected to a distinct column of memory cells. Having the columns of memory cells and local column lines divided into sectors allows for erase operations to be performed on sectors of memory cells. Main column lines are also used to route a signal appearing on a local column line to the periphery of array A without an appreciable time delay or signal degradation. The use of local and main column lines in flash memory devices is known in the art.
A row decoder R and column decoder C are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers SA are coupled to the main column lines to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of array A, the row and column decoders and sense amplifiers SA are known in the art and will not be described further for reasons of simplicity.
Redundancy has been previously utilized in flash memory devices to, among other things, replace columns of memory cells having a defect with redundant columns of memory cells so as to improve manufacturing yield. Redundant columns RC are disposed in or immediately adjacent each block B. Each block B has a distinct set of redundant columns RC, as shown in
FIG. 1. A
redundant column RC is adapted to replace a column of flash memory cells having a defect (i.e., a defective column) in the block B with which redundant column RC is associated. Nonvolatile storage components SC, which may be maintained in a secondary array of memory cells, are utilized to identify whether the redundant columns RC are used to replace a defective column.
In one existing flash memory design, defective regular columns of memory cells are individually replaced with redundant columns of memory cells. A single storage component SC is associated with a distinct redundant column RC. Each storage component SC is capable of storing the column address of the defective column that the associated redundant column RC replaces, together with an enable bit to enable the column replacement during a memory access operation. This type of existing flash memory device is thereby capable of individually replacing defective columns in the flash memory array A with redundant columns of redundant memory cells. This existing redundancy strategy is more efficient in overcoming random failures appearing in array A, and is less efficient in overcoming clusters of failures therein.
In another existing flash memory design, main column lines and the columns of memory cells associated therewith are replaced as a set. Specifically, a storage component is capable of identifying for replacement a main column line and columns of memory cells associated therewith in a single block, together with an enable bit to enable the replacement during a memory access operation. This type of existing flash memory device is thereby capable of replacing defective columns in a set with a set of redundant columns RC of redundant memory cells. This existing redundancy strategy is more efficient in overcoming clusters of failures appearing in array A and less efficient in handling random failures in array A. Both of the above-described existing flash memory designs are relat
Fasoli Luca Giovanni
Matarrese Stella
Auduong Gene N.
Jorgenson Lisa K.
Nelms David
STMicroelectronics Inc.
Szuwalski Andre
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