Redundancy and testing techniques for IC wafers

Details Redundancy and testing techniques for IC wafers Redundancy and testing techniques for IC wafers

1988-12-22

1990-11-13

Atkinson, Charles E.

Excavating

364900, 371 221, G06F 1120

Patent

active

049707248

ABSTRACT:
An array of processing element nodes are provided on a semiconductor wafer. A mixed redundancy approach is preferably employed wherein two spare core logic circuit modules 52, 58 are available for use at each node. Each spare core logic module can be connected to one of four different nodes. An H-net 94 interconnects adjacent nodes in such manner that faults in the circuit modules can be easily tested and repaired.

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