Redundancy and buffering circuits

Details Redundancy and buffering circuits Redundancy and buffering circuits

1988-03-02

1990-01-16

Atkinson, Charles E.

Excavating

371 34, G06F 1100

Patent

active

048948276

ABSTRACT:
This invention provides an improved means for communicating between a central communications or computer processor and a plurality of peripheral devices via a serial interface such as a pulse coded modulation (PCM) bus. The processor sends data via one of two redundant communications channels, such as a PCM bus, to the peripheral devices, each of which is equipped with a data receiving means such as a shift register. These data receiving means check a specific character position of the input data for a pattern which is unlikely to occur at random, such as hexadecimal `7E`. (X `7E` has a bit pattern of 0111 1110.) Whenever the specified pattern is detected, a return pattern is generated in a specified character position of the data stream which is periodically sent back to the processor. As long as these return characters are received, the processor continues to send data via the first communications channel, and the receiving peripheral devices continue to read their data from that channel. When the return pattern is not received, however, the redundance circuit recognizes this fact and switches to the other communications channel. The receiving means on the peripheral devices detect that the special pattern is now being received in the specified character position of the second communications data stream and switch to read data from the second channel. Thus the error-checking features of more complicated and expensive systems are provided without the need for sophisticated processors on the peripheral devices.

REFERENCES:
patent: 3453592 (1969-07-01), Ishii et al.
patent: 4011542 (1977-03-01), Baichtal et al.
patent: 4070648 (1978-01-01), Merganthaler et al.
patent: 4369516 (1983-01-01), Byrns
patent: 4633473 (1986-12-01), Ratchford et al.

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