Excavating
Patent
1993-01-29
1996-12-24
Beausoliel, Jr., Robert W.
Excavating
39518318, 371 211, 371 401, 3642431, 3642453, 3642683, G06F 1100
Patent
active
055881157
ABSTRACT:
Memory test apparatus including a redundancy analyzer with a catch RAM transfer interface circuit receiving fault information for a plurality of regions of a memory under test simultaneously in parallel and transmitting the information for each region to a respective one of a plurality of region modules that each has a region input circuit, a region fault RAM, and a microprocessor connected to have access to the region fault RAM, the region fault RAMs storing fault addresses identifying the locations of faults in the memory under test.
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Beausoliel, Jr. Robert W.
Le Dieu-Minh
Teradyne, Inc.
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