Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-07-30
2003-10-07
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C156S345120, C216S038000, C216S088000, C216S089000, C252S079100, C438S745000, C438S693000
Reexamination Certificate
active
06630403
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor wafer manufacturing and more particularly to improved composition, use and method for reduction of surface roughness of such wafers during chemical-mechanical planarization (CMP).
BACKGROUND OF THE INVENTION
Chemical-mechanical planarization (CMP) processes are applied in the manufacturing of integrated circuits and other electronic devices for the removal of unwanted material from the surface of semiconductor wafers and other microelectronic-device substrate assemblies. Additionally, the CMP processes are used in conjunction with the planarization and polishing of such surfaces subsequent to the deposition of layers of metal and insulation.
In particular, mechanical and chemical-mechanical planarization processes (“CMP”) are used in the manufacturing of electronic devices for forming a flat surface on semiconductor wafers, field emission displays and many other microelectronic-device substrate assemblies. CMP processes generally remove material from a wafer assembly to create a highly planar surface at a precise elevation in the layers of material on the wafer assembly. Referring to
FIG. 1
, there is shown a cross-sectional view of a portion of a CMP system
100
that includes wafer carrier assembly
104
, platen
106
, under-pad
108
, CMP pad
110
, CMP pad drive shaft
112
, motor
116
and motor/downward force applicator/sensor assembly
118
. CMP pad
110
is a conventional pad. In operation, wafer carrier assembly
104
maintains wafer assembly
120
in position for CMP in a manner known in the art. Additionally, polishing solution
102
is applied to CMP pad
110
for removing material from wafer assembly
120
.
Accordingly, CMP pad
110
and polishing solution
102
define a planarizing medium that mechanically and/or chemically-mechanically removes material from the surface of the wafer assembly
120
. In certain applications, CMP pad
110
may be a non-abrasive pad without abrasive particles, composed of a polymeric material (e.g., polyurethane) or other suitable materials. Polishing solution
120
used with the non-abrasive planarizing pads are typically CMP slurries with abrasive particles and chemicals to remove material from a substrate.
Further, CMP processing has moved to the use and application of CMP pads having higher modulus polyurethane pads to increase die uniformity and reduce the range of thickness variation across the wafer being polished. A major drawback to this process has been the propensity for these hard pads to be associated with a phenomenon referred to as “rough oxide” or “rough interlayer dielectric (ILD)”, especially on ILD polishes. Rough oxide is a condition where rough areas are created on the wafer, usually periodically spaced, in periphery (i.e., low topography) regions as the wafer is polished to planarity. This roughness can include a slurry gelation or removed glass redoposition at the surface. When such roughness becomes excessive, scratches can emanate from these regions causing “chatter scratches” that tend to cause localized cracking in the oxide (i.e., “wormholing”). In an ILD film, this “wormholing” can provide channeling of subsequent cleaning chemistries, such as Tetra Methyl Ammonia Hydroxide (TMAH), to underlying metal structures, thus creating metal voids in the integrated circuit within such wafers. Further, this roughness caused by the slurry properties is more apt to happen when the slurry particle has a large surface area with respect to its volume (i.e., a highly fractal structure (e.g., fumed silicas like ILD 1300) and/or a small diameter (e.g., small colloidal silicas like Klebosol 30N20)). Accordingly, this roughness phenomenon becomes worse with a combination of a small diameter and a high fractal nature with regard to the slurry particle.
Moreover, this “rough oxide” phenomenon can also happen while performing shallow trench isolation (STI) CMP processing. STI is not used in the creation of a planarized layer, but, rather, in the formation of planarized isolation features. With STI, scratching and cracking can cause an electrical leakage, pathway and/or electrical shorts. In particular, scratching at STI CMP can create voids in or elimination of the STI oxide, thereby reducing or eliminating the isolation in the silicon. Further, cracks in the oxide or underlying nitride CMP stop layer can cause damage to the base silicon. Accordingly, in subsequent processing steps, cracks or scratches in the oxide or base silicon may be filled with metal used during the formation of wordlines, thereby creating electrical shorts.
Accordingly, there is a need for compositions, uses and methods for reduction of surface roughness during chemical-mechanical planarization (CMP). For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above-mentioned problems and limitations associated with surface roughness during chemical-mechanical polishing (CMP) of semiconductor wafers and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Compositions, methods and use are described which accord improved benefits.
Improved methods, compositions and structures formed therefrom are provided that allow for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer. In one such embodiment, improved methods, compositions and structures formed therefrom for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer are used in conjunction with high modulus polyurethane pads. In one embodiment, improved methods, compositions and structures formed therefrom are provided that reduce rough interlayer dielectric (ILD) conditions for a wafer during CMP processing of such a wafer. Accordingly, this reduction of rough ILD reduces “chatter scratches” which are scratches that emanate from regions of a wafer that has undergone CMP processing. Advantageously, reduction in “chatter scratching” reduces cracking (i.e., “wormholing”) in layers of the wafer that have been planarized. Therefore, reduction in cracking decreases access of cleaning chemistries to underlying structures of the wafer during subsequent chemical cleaning of the planarized wafer, thereby reducing damage to such underlying structures from these cleaning chemistries (e.g., reduction of metal voids in underlying metal structures).
Moreover, in one embodiment, improved methods, compositions and structures formed therefrom are provided that reduces this roughness in layers of a planarized wafer used in conjunction with CMP shallow trench isolation (STI). Accordingly, this reduction of roughness reduces scratching and cracking of the layers (e.g., oxide layer or nitride CMP stop layer) of the planarized wafer during the STI process. Therefore, reduction in scratching and cracking of the layers reduces the formation of electrical shorts caused during the subsequent processing of the wafer when metal is layered for the formation of metallized layers (e.g., for the formation of wordlines).
Embodiments of a method for forming a microelectronic substrate include mixing a surfactant at least 100 parts per million (ppm) to slurries to form a polishing solution. The method also includes chemical-mechanical planarizing of the semiconductor wafer using the polishing solution. Additionally, embodiments of a polishing solution for chemical-mechanical planarizing a microelectronic substrate includes slurries and a surfactant at least 100 parts per million (ppm) to the slurries.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
Kramer Stephen J.
Meikle Scott G.
Micro)n Technology, Inc.
Powell William A.
Schwegman Lundberg Woessner & Kluth P.A.
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