Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-03-13
2010-06-08
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185240, C365S185330
Reexamination Certificate
active
07733705
ABSTRACT:
A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpassvoltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlowvoltage that is less than Vpass.
REFERENCES:
patent: 5257225 (1993-10-01), Lee
patent: 5357463 (1994-10-01), Kinney
patent: 5424993 (1995-06-01), Lee et al.
patent: 5511022 (1996-04-01), Yim et al.
patent: 5528547 (1996-06-01), Aritome et al.
patent: 5621684 (1997-04-01), Jung
patent: 5677873 (1997-10-01), Choi et al.
patent: 5677875 (1997-10-01), Yamagata
patent: 5680350 (1997-10-01), Lee
patent: 5715194 (1998-02-01), Hu
patent: 5768287 (1998-06-01), Norman et al.
patent: 5771346 (1998-06-01), Norman et al.
patent: 5907855 (1999-05-01), Norman
patent: 5917757 (1999-06-01), Lee et al.
patent: 5920501 (1999-07-01), Norman
patent: 5930168 (1999-07-01), Roohparvar
patent: 5959892 (1999-09-01), Lin
patent: 5991202 (1999-11-01), Derhacobian et al.
patent: 6061270 (2000-05-01), Choi
patent: 6107658 (2000-08-01), Itoh et al.
patent: 6157575 (2000-12-01), Choi
patent: 6163048 (2000-12-01), Hirose et al.
patent: 6240016 (2001-05-01), Haddad
patent: 6240023 (2001-05-01), Roohparvar
patent: 6370062 (2002-04-01), Choi
patent: 6380033 (2002-04-01), He et al.
patent: 6469933 (2002-10-01), Choi et al.
patent: 6487117 (2002-11-01), Choi et al.
patent: 6493270 (2002-12-01), Chevallier
patent: 6498752 (2002-12-01), Hsu et al.
patent: 6519181 (2003-02-01), Jeong
patent: 6522584 (2003-02-01), Chen et al.
patent: 6620682 (2003-09-01), Lee et al.
patent: 6657915 (2003-12-01), Seo et al.
patent: 6660585 (2003-12-01), Lee et al.
patent: 6661707 (2003-12-01), Choi et al.
patent: 6707714 (2004-03-01), Kawamura
patent: 6798694 (2004-09-01), Mihnea et al.
patent: 6925011 (2005-08-01), Pekny et al.
patent: 6975537 (2005-12-01), Lutze et al.
patent: 6977842 (2005-12-01), Nazarian
patent: 6982905 (2006-01-01), Nguyen
patent: 7020017 (2006-03-01), Chen et al.
patent: 7099193 (2006-08-01), Futatsuyama
patent: 7120059 (2006-10-01), Yeh
patent: 7161833 (2007-01-01), Hemink
patent: 7212435 (2007-05-01), Rudeck et
patent: 7245534 (2007-07-01), Goda et al.
patent: 7292476 (2007-11-01), Goda et al.
patent: 7355889 (2008-04-01), Hemink et al.
patent: 7394693 (2008-07-01), Aritome
patent: 7408810 (2008-08-01), Aritome et al.
patent: 7440321 (2008-10-01), Aritome
patent: 7471565 (2008-12-01), Aritome
patent: 7474560 (2009-01-01), Aritome
patent: 7499330 (2009-03-01), Goda et al.
patent: 7505322 (2009-03-01), Lee
patent: 7561469 (2009-07-01), Aritome
patent: 7570513 (2009-08-01), Li et al.
patent: 2002/0060926 (2002-05-01), Choi
patent: 2002/0075727 (2002-06-01), Jeong
patent: 2002/0149958 (2002-10-01), Kunikiyo
patent: 2004/0080980 (2004-04-01), Lee
patent: 2004/0152262 (2004-08-01), Ichige et al.
patent: 2004/0237000 (2004-11-01), Keays
patent: 2005/0088890 (2005-04-01), Matsunaga
patent: 2005/0226055 (2005-10-01), Guterman
patent: 2005/0265097 (2005-12-01), Tanaka et al.
patent: 2006/0002167 (2006-01-01), Rudeck et al.
patent: 2006/0023502 (2006-02-01), Cernea et al.
patent: 2006/0274583 (2006-12-01), Lutze
patent: 2007/0047314 (2007-03-01), Goda et al.
patent: 2007/0177429 (2007-08-01), Nagashima et al.
patent: 2007/0236992 (2007-10-01), Oowada
patent: 2007/0258286 (2007-11-01), Higashitani
patent: 2008/0101126 (2008-05-01), Hemink
patent: 2008/0253187 (2008-10-01), Aritome
patent: 2008/0316827 (2008-12-01), Higashitani
patent: 2009/0189211 (2009-07-01), Orimoto et al.
S. Satoh et al., A Novel Gate-Offset NAND Cell (Goc-NAND) Technology Suitable for High-Density and Low-Voltage-Operation Flash Memories, Microelectronics Engineering Laboratory, Japan, IEEE, 1999, 4 pgs.
S. Satoh et al., A Novel Isolation-Scaling Technology for NAND EEPROMs with the Minimized Program Disturbance, Microelectronics Engineering Laboratory, Japan, IEEE, 1997, IEDM 97-291, pp. 11.6.1-11.6.4.
T. Jung et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications” IEEE Journal of Solid-State Circuits, IEEE Inc., New York, NY, U.S., vol. 31, No. 11, Nov. 1996, pp. 1575-1583.
K. Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme” IEEE Journal of Solid-State Circuits, IEEE Inc., New York, NY, vol. 30, No. 11, Nov. 1995, pp. 1149-1156.
Aritome Seiichi
Musilli Carlo
Torsi Alessandro
Leffert Jay & Polglaze P.A.
Luu Pho M.
Micro)n Technology, Inc.
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