Reduction of parasitic through hole via capacitance in multilaye

Details Reduction of parasitic through hole via capacitance in multilaye Reduction of parasitic through hole via capacitance in multilaye

1997-08-01

2000-10-24

Gaffin, Jeffrey

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174266, 361795, H05K 116

Patent

active

061370614

ABSTRACT:
A printed circuit board that reduces parasitic effects on devices mounted thereon. The printed circuit board comprises a top layer and a bottom layer of a first insulating material having a first dielectric constant. The layers are configured to form holes whereby each of the holes has a first part extending through the top layer and a second part extending through the bottom layer. The bottom layer is further configured to comprise a second insulating material having a second dielectric constant, which second insulating material surrounds the second part of the hole. The devices mounted onto the printed circuit board have pins that extend through the holes. When the second dielectric constant is less than the first dielectric constant, the parasitic effects on the pins of the mounted devices are reduced.

REFERENCES:
patent: 3792383 (1974-02-01), Knappenberger
patent: 4641426 (1987-02-01), Hartman et al.
patent: 5065284 (1991-11-01), Hernandez

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