Reduction of mechanical stress in shallow trench isolation...

Details Reduction of mechanical stress in shallow trench isolation... Reduction of mechanical stress in shallow trench isolation...

1998-11-13

2001-04-24

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000, C438S435000, C148SDIG005

Reexamination Certificate

active

06221733

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to methods for fabricating semiconductor integrated circuits such as memory devices and more particularly, it relates to a method of minimizing or eliminating mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation process.
2. Description of the Prior Art
As is generally known, in the manufacturing of semi-conductor integrated circuits there is typically required isolation of devices (active regions) from one another which are formed on a semiconductor substrate. One such isolation technique is known as LOCOS (local oxidation of silicon) where an isolation region is grown on the substrate between the active regions by thermal oxidation. However, in view of the advances made in semiconductor integrated circuit technology and reduction of device sizes so as to achieve higher density, it has been found that a newer isolation method referred to as “shallow trench isolation” (STI) has become the replacement for the conventional LOCOS technology for sub-micron process technology. In the basic STI technology, there is involved the etching of the semiconductor substrate in order to form trenches and thereafter the re-filling of the trenches with an insulating material so as to produce an isolation region.
While it is desirable to use silicon dioxide layers as trench fill dielectric layers within advanced integrated circuit fabrication, it is generally known that such trench-refilling oxide may shrink during subsequent fabrication steps (e.g., thermal annealing) which will cause mechanical stress in the active silicon substrate. This mechanical stress is believed to cause the generation of dislocations or defect sites in the active substrate. This problem is discussed in a paper entitled “Mechanical Stress Induced MOSFET Punch-Through and Process Optimization for Deep Submicron TEOS-O
3
Filled STI Device,” by K. Ishimaru et al., 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 123-124.
Further, in one case investigated it was found that there existed a high leakage current path along the source and drain regions of a transistor device formed during subsequent steps in the substrate, thereby rendering a lower produce yield. While there have been many attempts made in the prior art of creating various process fixes so as to solve this mechanical stress problem, most of the proposed process changes have suffered from the disadvantages of causing some other types of detrimental effects or have been generally not suitable for application involving non-volatile memory technology.
Accordingly, it would be desirable to provide a method of minimizing or eliminating mechanical stress in current standard STI process on a more effective and efficient basis. This is achieved in the present invention by either, (a) forming a trench with a more sloped and smooth profile, (b) limiting the trench depth to be less than 0.4 &mgr;m, (c) reducing or increasing the trench densification temperature, and/or (d) performing the densification step after chemical-mechanical polishing.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a method of minimizing or eliminating mechanical stress in a standard STI process which overcomes the problems of the prior art.
It is an object of the present invention to provide a method of minimizing or eliminating mechanical stress in a standard STI process which can be implemented with only minor modifications to the same.
It is another object of the present invention to provide a method of minimizing mechanical stress in a standard STI process which includes forming trenches with a more sloped and smooth profile.
It is still another object of the present invention to provide a method of minimizing mechanical stress in a standard STI process which includes either reducing or increasing the trench densification temperature.
It is yet another object of the present invention to provide a method of minimizing mechanical stress in a standard STI process which includes the step of performing a densification after the chemical-mechanical polishing step.
In accordance with a preferred embodiment of the present invention, there is provided a method of minimizing or eliminating mechanical stress in a standard shallow trench isolation (STI) process. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. A plurality of trenches are formed through the nitride layer and the barrier oxide layer and into the epitaxial layer to a depth of less than 4,000 Å so as to create isolation regions to electrically isolate active regions in the epitaxial layer from each other. A liner oxide layer is formed on the sidewalls and bottom of the trenches.
The trenches are filled completely with a trenchfilling material which has less volume shrinkage coefficient than an ozone-TEOS film to form an oxide layer. The oxide layer is polished away down to the top surface of the nitride layer. Thermal annealing is performed on the substrate subsequent to the polishing of the oxide layer.


REFERENCES:
patent: 4389294 (1983-06-01), Anantha et al.
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 5200348 (1993-04-01), Uchida et al.
patent: 5985735 (1999-11-01), Moon et al.

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