Reduction of leakage current and program disturbs in flash...

Details Reduction of leakage current and program disturbs in flash... Reduction of leakage current and program disturbs in flash...

2006-04-05

2009-02-10

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185270, C365S189090

Reexamination Certificate

active

07489560

ABSTRACT:
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a negative substrate bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. The negative substrate bias voltage also reduces the occurrence of program disturbs in cells adjacent to target cells by extending the depletion region deeper below the bit line that corresponds to the drain of the target device. The negative substrate bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce error in the verification operations.

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PCT Search Report for PCT/US07/08576, Nov. 22, 2007, Spansion LLC.
PCT Written Opinion for PCT/US07/08576, Nov. 22, 2007, Spansion LLC.

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