Reduction of gate oxide breakdown for booted nodes in MOS integr

Details Reduction of gate oxide breakdown for booted nodes in MOS integr Reduction of gate oxide breakdown for booted nodes in MOS integr

1982-09-16

1985-04-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307481, 307578, 307269, H03K 1708, H03K 1710, H03K 17687

Patent

active

045089787

ABSTRACT:
In a clock generator circuit for a dynamic RAM or the like it is necessary to boot certain nodes to a value to above the supply voltage in order to provide a high-level gate voltage for output transistors. To prevent excess voltage on the gate oxide of a transistor connected to a booted node, a series transistor is added which has the supply voltage on its gate, so neither transistor will have the full booted voltage across its gate oxide.

REFERENCES:
patent: 3818245 (1974-06-01), Suzuki et al.
patent: 4051388 (1977-09-01), Inukai
patent: 4199695 (1980-04-01), Cook et al.
patent: 4239990 (1980-12-01), Hong et al.
patent: 4239991 (1980-12-01), Hong et al.
patent: 4379974 (1983-04-01), Plachno

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