Reduction of dynamic DC offsets in a wireless receiver

Telecommunications – Receiver or analog modulated signal frequency converter

Reexamination Certificate

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Details

C455S232100, C455S234100, C455S242200, C375S345000

Reexamination Certificate

active

10770947

ABSTRACT:
A gain control system in a Direct Conversion Receiver or similar receiver, includes an automatic gain control circuit which determines whether a low noise amplifier, which amplifies signals from an antenna prior to mixing with signals from a local oscillator, should be set to a high gain or a low gain. The output of the mixer is analyzed by a blocker detect circuit to determine whether a blocker signal is present. Based on the presence of a blocker signal and the power level of the useful signal, the gain of the low noise amplifier may be reduced from the high gain to an intermediate gain in order to reduce self mixing between the radio frequency and local oscillator ports of the mixer, which may lead to dynamic DC offsets.

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patent: 6442380 (2002-08-01), Mohindra
patent: 6571083 (2003-05-01), Powell et al.
patent: 6980786 (2005-12-01), Groe
patent: 2002/0142745 (2002-10-01), Kang et al.
patent: 2003/0025623 (2003-02-01), Brueske et al.
patent: 2003/0064692 (2003-04-01), Shi
patent: 2004/0152432 (2004-08-01), Gu
patent: 2005/0047533 (2005-03-01), Ruelke et al.

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