Reduction of dislocations in a heteroepitaxial semiconductor str

Details Reduction of dislocations in a heteroepitaxial semiconductor str Reduction of dislocations in a heteroepitaxial semiconductor str

1995-09-05

2000-01-04

Bowers, Charles

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including isolation structure

438413, 438495, H01L 21331

Patent

active

060109378

ABSTRACT:
A heteroepitaxial semiconductor device having reduced density of threading dislocations and a process for forming such a device. According to one embodiment, the device includes a substrate which is heat treated to a temperature in excess of 1000.degree. C., a film of arsenic formed on the substrate at a temperature between 800.degree. C. and 840.degree. C., a GaAs nucleation layer of less than 200 angstroms and formed at a temperature between about 350.degree. C. and 450.degree. C., and a plurality of stacked groups of layers of InP, wherein adjacent InP layers are formed at different temperatures.

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