Reduction of chip carrier flexing during thermal cycling

Details Reduction of chip carrier flexing during thermal cycling Reduction of chip carrier flexing during thermal cycling

2002-09-30

2004-11-16

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With means for controlling lead tension

C257S668000, C257S669000, C257S746000, C257S747000

Reexamination Certificate

active

06818972

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and structure for reducing chip carrier flexing during thermal cycling.
2. Related Art
A semiconductor chip may be mechanically and conductively coupled to a chip carrier by having conductive contacts on the chip (e.g., Controlled Collapse Chip Connection solder balls) solderably coupled to the top surface of the chip carrier. During processing steps that elevate the temperature of the chip carrier, such as during a reflow step for solderably joining the chip to the chip carrier, a spatial distribution of coefficient of thermal expansion (CTE) due to material inhomogeneities within the chip carrier may cause the chip carrier to bow (or flex) upward or downward and thus deviate from planarity. For example, there may be large copper pads on the bottom of the chip carrier to accommodate a ball grid array of solder balls for coupling the chip carrier to a circuit card, and smaller amounts of copper, such as in the form of copper circuitization and/or copper pads for joining a chip to the chip carrier on the top surface of the chip carrier. The spatial distribution of CTE, and consequent bowing or sagging of the chip carrier when the chip carrier is heated, is a result of copper imbalance between the top and bottom surfaces of the chip carrier combined with volumetric distribution within the chip carrier of materials having different magnitudes of CTE.
The preceding chip carrier flexing problem increases in severity if the chip carrier is made of compliant material, such as compliant organic material which cannot be easily handled (e.g., a material having an elastic modulus of less than about 300,000 psi). An organic chip carrier that is highly compliant may benefit from a rigid “stiffener ring” bonded to an outer perimeter of the top surface of the chip carrier in order to enhance the structural characteristics of the chip carrier. That is, the stiffener ring makes the chip carrier more mechanically stable and thus easier to handle. Unfortunately, the stiffener ring acts as a mechanical clamp on the outer perimeter of the chip carrier that constrains outer portions of the chip carrier from expanding, particularly when subjected to elevated temperature. In contrast, center portions of chip carrier at which chips are typically attached, are not constrained by the stiffener ring. Thus, expansion of the central portions, when heated, accentuates the chip carrier bowing by causing a distinct upward bulge in the central portion of the chip carrier top surface.
An adverse consequence of chip carrier bowing, particularly when a stiffener ring is used with a compliant organic chip carrier, is unreliable coupling of a chip to the chip carrier, as illustrated in
FIGS. 1 and 2
.
FIG. 1
shows a semiconductor chip
10
resting on an organic chip carrier
20
at ambient room temperature, wherein a top surface
14
of the chip carrier
20
is flat, and wherein solder balls
11
,
12
, and
13
on the semiconductor chip
10
are in conductive contact with solder bumps
24
,
25
, and
26
at the conductive pads
17
,
18
, and
19
on the top surface
14
of the chip carrier
20
, respectively. A stiffener ring
15
is bonded to the outer perimeter of the chip carrier
20
by an interfacing adhesive
16
.
FIG. 2
shows the chip carrier
20
of
FIG. 1
under temperature elevation, such as when solder from the solder bumps
24
,
25
, and
26
is reflowed around the solder balls
11
,
12
, and
13
in an attempt to conductively join the solder balls
11
,
12
, and
13
to the conductive pads
17
,
18
, and
19
, respectively. At the elevated temperature, the center the chip carrier
20
is bows (or bulges) upward in the direction
22
, such that the solder balls
11
and
13
are no longer in conductive contact with the conductive pads
17
and
19
, respectively. Thus, the chip carrier flexing impairs the ability to reliably join a chip to a chip carrier. The bowing B may exceed 2 to 3 mils during solder reflow.
A method and structure is needed for reducing or eliminating flexing of a compliant organic chip carrier in an elevated temperature environment, and particularly when solder is reflowed around solder balls of a semiconductor chip for joining the semiconductor chip to the chip carrier.
The related art does not teach or suggest how to reduce flexing of a stiff chip carrier during thermal cycling. As a result, a stiff chip carrier may experience flexing that leads to cracking during thermal cycling.
A method and structure is therefore needed for reducing chip carrier flexing during thermal cycling.
SUMMARY OF THE INVENTION
The present invention provides an electronic structure, comprising:
a chip carrier having an elastic modulus of at least about 3×10
5
psi, wherein there is no stiffener ring coupled to a peripheral portion of the chip carrier; and
a semiconductor chip coupled to a central portion of the chip carrier.
The present invention provides a method of forming an electronic structure, comprising:
providing a chip carrier having an elastic modulus of at least about 3×10
5
psi, wherein there is no stiffener ring coupled to a peripheral portion of the chip carrier; and
coupling a semiconductor chip to a central portion of the chip carrier.
The present invention improves an ability of a stiff chip carrier to accommodate stresses thermally induced in the chip carrier during thermal in order to reduce or eliminate flexing of the chip carrier during the thermal cycling.


REFERENCES:
patent: 5136470 (1992-08-01), Sheridon et al.
patent: 5450286 (1995-09-01), Jacques et al.
patent: 5571608 (1996-11-01), Swamy
patent: 5760465 (1998-06-01), Alcoe et al.
patent: 5773884 (1998-06-01), Andros et al.
patent: 5877043 (1999-03-01), Alcoe et al.
patent: 5987742 (1999-11-01), Acciai et al.
patent: 6014317 (2000-01-01), Sylvester
patent: 6027590 (2000-02-01), Sylvester et al.
patent: 6528179 (2003-03-01), Jimarez et al.
patent: 11-274736 (1999-10-01), None
Japanese Patent Publication No. 11-274736 Japanese Patent Office Computer Translation, Oct. 8, 1999, Shinada et al., 21 pages.*
Multi-Layer Substrate with Low Coefficent of Thermal Expansion, Nakamura et al., 2000 International Symposium on Microelect, pp. 235-240.

Affiliated with

Also associated with

Rating

Reduction of chip carrier flexing during thermal cycling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduction of chip carrier flexing during thermal cycling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduction of chip carrier flexing during thermal cycling will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3315834