Reduction of base-collector junction parasitic capacitance of he

Details Reduction of base-collector junction parasitic capacitance of he Reduction of base-collector junction parasitic capacitance of he

1994-03-10

1995-11-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437133, H01L 21265, H01L 2120

Patent

active

054686598

ABSTRACT:
A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.

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Mau-Chung F. Chang et al, "AlGaAs/GaAs Heterojunction Bipolar Transistors Fabricated Using A Self-Aligned Dual-Lift-Off Process", IEEE Electron Device Letters, vol. EDL-8, No. 7, pp. 303-305 (Jul. 1987).
T. R. Followan et al, "High Yield Scalable Dry Etch Process for Indium Based Heterojunction Bipolar Transistors", Proceedings of InP and Related Materials Conference, WP15, pp. 343-346 (1992).

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