Reduction of adjacent floating gate data pattern sensitivity

Details Reduction of adjacent floating gate data pattern sensitivity Reduction of adjacent floating gate data pattern sensitivity

2008-06-10

2008-06-10

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185020

Reexamination Certificate

active

07385846

ABSTRACT:
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.

REFERENCES:
patent: 5543339 (1996-08-01), Roth
patent: 6046086 (2000-04-01), Lin
patent: 6388919 (2002-05-01), Terasaki
patent: 6781877 (2004-08-01), Cernea et al.
patent: 6987694 (2006-01-01), Lee

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