Reducing voltage variation in a phase locked loop

Details Reducing voltage variation in a phase locked loop Reducing voltage variation in a phase locked loop

2001-10-16

2003-10-28

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S551000

Reexamination Certificate

active

06639439

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to circuit design. More particularly, this invention relates to a method for reducing voltage variation in a phase locked loop.
2. Background Art
In electronic circuits, the system power supply can be shown as an equivalent circuit
10
as shown in FIG.
1
. Specifically, the equivalent circuit
10
includes: a system power supply source
12
; a system resistance (Rs)
14
; a system inductance (Ls)
16
; and a chip capacitance (Rc)
18
. Each of these system components
12
,
14
,
16
, and
18
represent an equivalent value of all of the combined respective components in the power supply system. The performance of the circuit
10
is frequency dependent. As shown in the graph of
FIG. 2
, as the frequency of the system increases, the resistance of the circuit increases as well. This increase in resistance continues until a peak
20
is reached at a resonance frequency. Finally, the resistance will subside at even higher frequencies.
The rate of increase in the resistance of the circuit as the frequency approaches its resonance value is quantified as a “Q” value. The “Q” value is calculated as Q=((L/C))/R; where L is the system inductance value; where C is the system capacitance value; and where R is the system resistance value. As shown in
FIG. 2
, under normal operations, the equivalent circuit
10
has a very high Q value
24
near the resonance frequency. A high current transient with the high Q region of the frequency band causes significant noise in the power supply system. Supply noise can result in such problems as voltage variation, signal jitter, signal stability, component or logic malfunction, signal interference, etc. For instance, a PLL circuit will have more jitter in the presence of power supply noise, which effectively leads to a reduction in the speed at which a chip can operate. Further, voltage variation is a significant problem because the indeterministic distribution of power to system components can lead to a loss of system performance.
It would be advantageous to decrease the Q value of the power supply system and thereby reduce voltage variation. A reduced Q value
26
is also shown in FIG.
2
. This Q value
26
would have the advantage of substantially reducing the voltage variation of the respective system.
FIG. 3
shows a prior art method of reducing the Q value for a phase locked loop (“PLL”) power supply system. A phase locked loop
32
is a component that may be included in an integrated circuit or “chip”. The phase locked-loop
32
is essentially a clock driver that uses feedback to output a clock signal such the clock signal output has a specific phase and frequency relationship to an input signal. Typically, a PLL
32
is used to align a reference clock with a chip clock. This is necessary to ensure proper and synchronized operation of components within a computer system. The phase locked loop
32
is just one of many types of components that are commonly included in an integrated circuit. Each of these components often has a dedicated power supply that is unique and separate from the power supplies of other components. The prior art method used in
FIG. 3
involves inserting a decoupling capacitor
34
across the power supply in parallel with the phase locked loop
32
. However, the capacitor
34
takes up a significant amount of space on the chip. With chip space at a premium, a space efficient method of reducing voltage variation for a phase locked loop is needed.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for reducing voltage variation in a phase locked loop comprising supplying power to the phase locked loop and connecting a resistance in parallel with the phase locked loop.
According to another aspect, a method for reducing voltage variation in a phase locked loop comprises step of supplying power to the phase locked loop and step of shunting a resistance in parallel with the phase locked loop.
According to another aspect, an apparatus for decreasing clock jitter in a phase locked loop comprises a phase locked loop, a power supply system connected to the phase locked loop, and a shunting resistor connected across the power supply system in parallel with the phase locked loop.
According to another aspect, an apparatus for reducing voltage variation in a phase locked loop comprises means of supplying power to a phase locked loop, and means of connecting an impedance in parallel with the phase locked loop.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5627736 (1997-05-01), Taylor
patent: 5949279 (1999-09-01), Kwan

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