Reducing variation in reference voltage when the load varies...

Details Reducing variation in reference voltage when the load varies... Reducing variation in reference voltage when the load varies...

2007-04-24

2007-04-24

Nguyen, Linh (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000, C341S121000, C341S172000

Reexamination Certificate

active

11161253

ABSTRACT:
Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.

REFERENCES:
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patent: 5451950 (1995-09-01), Vincelette et al.
patent: 6559787 (2003-05-01), Aude et al.
patent: 6836228 (2004-12-01), Levinson et al.
patent: 6906658 (2005-06-01), Pentakota et al.
patent: 7095356 (2006-08-01), Pentakota et al.
patent: 2006/0038712 (2006-02-01), Harrison et al.

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