Reducing the time to convert an analog input sample to a...

Details Reducing the time to convert an analog input sample to a... Reducing the time to convert an analog input sample to a...

2007-11-02

2009-08-18

Nguyen, Linh V (Department: 2819)

Coded data generation or conversion

Sample and hold

C341S118000, C341S120000, C341S155000, C341S161000, C341S162000

Reexamination Certificate

active

07576668

ABSTRACT:
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

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