Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2007-12-18
2007-12-18
Nguyen, Linh (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S122000
Reexamination Certificate
active
11160859
ABSTRACT:
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
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Sotirios Limotyrakis, Scott D. Kulchycki, David K. Su, and Bruce A. Wooley, “A 150-MS/s 8-b 71-mW CMOS Time-Interleaved ADC”, IEEE Journal of Solid-State Circuits, May 2005, pp. 1057-1067 (10 Pages), vol. 40, No. 5.
Agarwal Nitin
Oswal Sandeep
Pentakota Visvesvaraya A.
Sinha Vikas Kumar
Udupa Anand Hariraj
Brady III Wade J.
Nguyen Linh
Telecky , Jr. Frederick J.
Texas Instruments (India) Private Limited Texas Instruments Inco
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