Reducing the number of power and ground pins required to...

Details Reducing the number of power and ground pins required to... Reducing the number of power and ground pins required to...

2007-10-30

2007-10-30

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Powering

C365S230030, C365S191000

Reexamination Certificate

active

10925174

ABSTRACT:
One embodiment of the present invention provides a system that reduces the number of power and ground pins required to drive address signals to system memory. During operation, the system receives address signals associated with a memory operation from a memory controller, wherein the address signals are received at a buffer chip, which is external the memory controller. The system also receives chip select signals associated with the memory operation at the buffer chip. Next, the system uses the chip select signals to identify an active subset of memory modules in the system memory, which are active during the memory operation. The system then uses address drivers on the buffer chip to drive the address signals only to the active subset of memory modules, and not to other memory modules in the system memory. In this way, the buffer chip requires fewer power and ground pins for the address drivers because the address signals are only driven to the active subset of memory modules, instead of being driven to all memory modules in the system memory.

REFERENCES:
patent: 5280590 (1994-01-01), Pleva et al.
patent: 5956288 (1999-09-01), Bermingham et al.
patent: 6556506 (2003-04-01), Naven
patent: 6697387 (2004-02-01), Larson
patent: 7024518 (2006-04-01), Halbert et al.
patent: 2006/0041713 (2006-02-01), Charles et al.

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