Reducing the number of executed branch instructions in a code se

Details Reducing the number of executed branch instructions in a code se Reducing the number of executed branch instructions in a code se

1996-11-12

1998-12-15

Trammell, James P.

395580, 395581, 395583, G06F 945

Patent

active

058505539

ABSTRACT:
A compiler technique for reducing the number of executed branches in a code sequence. Multiple condition branch instructions in a program sequence are replaced with a single combined conditional branch instruction thereby eliminating the time-consuming execution of multiple branch instructions by a target processor.

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Bernstein et al., Performance Evaluation of Instruction Scheduling on the IBM RISC System/16000, Proc. 25th Ann. Intl. Symp. on Microarchitecture, Dec. 1992, IEEE Comp. Soc. Press, pp. 226-235.

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