Reducing stress in integrated circuits

Details Reducing stress in integrated circuits Reducing stress in integrated circuits

2002-12-31

2004-11-09

Flynn, Nathan J. (Department: 2826)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S014000

Reexamination Certificate

active

06815234

ABSTRACT:

BACKGROUND OF INVENTION
FIG. 1
shows an integrated circuit chip
101
. The chip comprises an IC
130
formed on a surface of a substrate
110
. The IC comprises various components, such as transistors, resistors and capacitors. The components are interconnected to create the desired functions. One or more passivation layers can be provided over the components for protection from, for example, moisture.
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT) are used to form certain components, such as capacitors. The capacitors can be used to form ferroelectric memory cells. A ferroelectric memory cell stores information in the capacitor as remanent polarization. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. An advantage of the ferroelectric memory cell is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
The various materials of the IC, after processing, may produce an overall stress (referred to as remaining stress). The remaining stress, for example, can be tensile stress (e.g., expansive). Such remaining stress can create bowing in the substrate on which the IC is formed, as shown in FIG.
2
. However, some components, such as ferroelectric capacitors, have been found to be very sensitive to mechanical stress. For example, local stress in the ferroelectric devices has been found to adversely impact device performance and reliability.
From the foregoing discussion, it is desirable to provide an IC which avoids the adverse impact of stress resulting from processing.
SUMMARY OF INVENTION
The invention relates to semiconductor processing. In particular, the invention relates to compensating for stress on a substrate resulting from semiconductor processing. In one embodiment, a semiconductor chip comprising an IC formed on a first surface of a substrate. The IC produces a remaining stress of a first type on the substrate. On a second surface of the substrate, a stress compensating layer is provided. The stress compensating layer produces a stress of a second type, which is opposite of the remaining stress. As a result, the stress compensating layer reduces the effective stress on the ferroelectric device, thus compensating for stress which can adversely affect performance and reliability.
In one embodiment, the stress compensating layer comprises a dielectric layer. The dielectric layer preferably comprises silicon nitride or silicon oxide. In a preferred embodiment, the dielectric material is deposited using plasma enhanced CVD. Such techniques advantageously enable the stress compensating layer to be tuned with specific stress characteristics.


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