Reducing stall delay in pipelined computer system using queue be

Details Reducing stall delay in pipelined computer system using queue be Reducing stall delay in pipelined computer system using queue be

1993-08-09

1994-06-28

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 3642615, 3642631, 3642386, 3642624, 3642318, 395800, G06F 938

Patent

active

053254953

ABSTRACT:
A pipelined computer system employs a queue stage to receive the output of one pipeline stage when a stall occurs in the next stage or downstream of the next stage. This avoids stalling earlier stages of the pipeline. Subsequently, the pipeline advances through the queue, until a bubble occurs. When a bubble is subsequently generated upstream and enters the queue stage, a multiplexer switches the input of the next stage to receive the output of the one stage instead of from the queue stage, and the content of the queue is overwritten. By this mechanism, the delays inherent in processing branches can be reduced.

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