Reducing sneak currents in virtual ground memory arrays

Details Reducing sneak currents in virtual ground memory arrays Reducing sneak currents in virtual ground memory arrays

2007-09-04

2007-09-04

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230060

Reexamination Certificate

active

11103064

ABSTRACT:
Sneak currents may be reduced between adjacent input/output groups in addressed memory arrays, even in the case when I/O breaks are ineffective, such as during erase verify. By providing a plurality of intervening, appropriately biased, non-addressed memory cells, a high resistance to sneak currents may be presented.

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U.S. Appl. No. 11/167,354, filed Jun. 27, 2005, Ruili Zhang et al.,Reducing Sneak Currents In Virtual Ground Memory Arrays.

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