Reducing signal swing in a match detection circuit

Details Reducing signal swing in a match detection circuit Reducing signal swing in a match detection circuit

2005-08-30

2005-08-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S154000, C365S189070, C365S189090

Reexamination Certificate

active

06937492

ABSTRACT:
The present invention provides a content addressable memory (CAM) match detection circuit that maintains traditionally achieved levels of accuracy while greatly reducing the amount of power dissipated. In accordance with an exemplary embodiment of the invention, rather than allowing the Matchline voltage to swing between a precharge voltage level (e.g., VDD) and Ground, the Matchline voltage is restricted to swinging between the precharge voltage level (e.g., VDD) and a Negative Reference voltage level that is lower than the precharge voltage level but higher than Ground.

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“A 250mV Bit-Line Swing Scheme for a 1V 4Gb DRAM,” T. Inaba et al., 1995 Symposium on VLSI Circuits Diges1 of Technical Papers, pp. 99 and 100.

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