Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2002-06-13
2003-12-02
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S637000, C257S758000
Reexamination Certificate
active
06657283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and particularly relates to reducing the relative stress between a passivation layer and a high density plasma layer that is formed with a high density plasma.
2. Description of the Prior Art
In fabrication of integrated circuit (IC) that comprises a substrate and at least a set of interconnects, a passivation layer is formed over the entire top surface of the substrate. This is an insulating, protective layer that prevents mechanical and chemical damages during assembly and packaging.
In general, passivation layer must satisfy following desired properties:
(1) provides good scratch protection to underling structures.
(2) Impermeable to moisture.
(3) Exhibits low stress.
(4) Conformal step coverage.
(5) High thickness uniformity.
(6) Impermeable to sodium atoms and other high mobile impurities.
(7) Easily patterned.
(8) Good adhesion to conductor.
A serious defection of passivation layer is owing to the fact that passivation layer is broadly formed by chemical vapor deposition (CVD) process in contemporary technique. Therefore, the coverage ability of CVD induces a disadvantage that adjacent conductive lines on top surface of integrated circuit may be not properly isolate by the passivation layer, which is more serious when integration of the integrated circuit is increased.
Referring to
FIG. 1
where a roughly illustration of cross-section view of an integrated circuit with some disadvantages is provided. Isolation
11
, gate
12
, spacer
13
, source
14
and drain
15
are located in and on substrate
10
. Beside, interconnects
16
, contacts
17
and dielectric layers
18
are formed on substrate to provide required metallization structure. Additionally, conductive lines
19
are formed on the metallization structure and affected as interconnects. Therefore, when passivation layer
193
is formed on the metallization structure by CVD, owing to the coverage of CVD, it is possible that void
196
is formed between two adjacent conductive lines
19
and increases the risk that adjacent conductive lines
19
are not properly isolated.
A well-known method, which is broadly applied in fabrication of integrated circuit that critical dimension is less than 0.5 m, to overcome the previous disadvantage is forming passivation layer
196
that directly covers conductive lines
19
by CVD with a high density plasma, as shown in FIG.
2
. Characteristic of the method is that during deposition, a DC bias is applied on wafer and then particles of plasma such as Ar will collide the deposited high density plasma layer
195
. Therefore, owing to the fact that colliding frequency is proportional to the electric field and the field is larger in edges of high density plasma layer
195
, hinges of high density plasma layer
195
is eliminated by collision and then no void is formed. Incidentally, owing to the fact the colliding frequency is larger in the edge and is smaller in the top, the thickness of high density plasma layer
195
is not uniform even it covers a smooth surface.
No matter how, owing to the truth that high density plasma layer
195
can not properly protect permeation of wafer and gas. An improved method is provided that passivation layer
193
is formed on high density plasma layer
195
to improve quality of passivation of integrated circuit. In other words, an integrated circuit is protected by a complex passivation layer that is formed by HDP and deposition in sequence.
However, an inevitable disadvantage of the improved method is that the absolute value of relative stress between high density plasma layer
195
and passivation layer
193
is about 1.8E08 dynes/cm
2
, such a high relative stress increases the risk that passivation of integrated circuit is degraded by cracks and pealing of passivation.
FIG. 3
shows the possible result of high relative stress. Where there are a plurality of cracks and pealing in passivation layer
193
, and other parts of the integrated circuit are omitted.
Therefore, it is indisputable that development of a new structure of passivation to overcome the disadvantage of high relative stress is desired, and the new structure of passivation is more important as high density plasma layer
195
is irreplaceable.
SUMMARY OF THE INVENTION
It is an object of the invention to propose some structures that efficiently prevent crack and pealing which are induced by high relative stress.
It is another object of the invention to provide some structures that prevent formation of void by employing a high density passivation layer (HDP layer) which is formed by high density plasma.
It is a further object of the invention to provide some structures that are manufacturable.
In order to realize of the invention, some structures are provided. These structures can be divided into two main categories:
First category, a low stress passivation layer is directly formed on a HDP layer.
Second category, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers.
Therefore, possible structures of the invention comprise following varieties:
First, a low stress passivation layer is located between a passivation layer and a HDP layer.
Second, a lower stress passivation layer directly locates on a HDP layer.
Third, a low stress layer is formed between a passivation layer and a HDP layer.
REFERENCES:
patent: 6426546 (2002-07-01), Chen et al.
Chen Ing-Tang
Lee Ellis
Lu Horng-Bor
Cao Phat X.
Dickinson Wright PLLC
Doan Theresa T.
United Microelectronics Corp.
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