Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2007-10-02
2007-10-02
Steelman, Mary (Department: 2191)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S130000, C717S140000, C711S170000
Reexamination Certificate
active
10191774
ABSTRACT:
A method, for use in a processor, includes mapping a first data access having less than a predetermined memory footprint to a first memory area, and mapping a second data access having greater than the predetermined memory footprint to a second memory area. The method may also include compiling computer code, inserting annotations into an intermediate representation of the computer code generated during compiling, propagating the annotations from the intermediate representation to a low-level representation of the computer code generated during compiling, and inserting instructions into the low-level representation, the instructions controlling mapping of the first data and the second data.
REFERENCES:
patent: 5410669 (1995-04-01), Biggs et al.
patent: 5579520 (1996-11-01), Bennett
patent: 5630143 (1997-05-01), Maher et al.
patent: 5655124 (1997-08-01), Lin
patent: 5704053 (1997-12-01), Santhanam
patent: 5774685 (1998-06-01), Dubey
patent: 5805907 (1998-09-01), Loper et al.
patent: 5857104 (1999-01-01), Natarjan et al.
patent: 5864697 (1999-01-01), Shiell
patent: 5875464 (1999-02-01), Kirk
patent: 5933860 (1999-08-01), Emer et al.
patent: 5949995 (1999-09-01), Freeman
patent: 5966544 (1999-10-01), Sager
patent: 6078745 (2000-06-01), De Greef et al.
patent: 6105139 (2000-08-01), Dey et al.
patent: 6219796 (2001-04-01), Bartley
patent: 6256743 (2001-07-01), Lin
patent: 6272676 (2001-08-01), Haghighat et al.
patent: 6334175 (2001-12-01), Chih
patent: 6393520 (2002-05-01), Yoshikawa et al.
patent: 6412105 (2002-06-01), Maslennikov et al.
patent: 6430693 (2002-08-01), Lin
patent: 6446181 (2002-09-01), Ramagopal et al.
patent: 6487640 (2002-11-01), Lipasti
patent: 6529943 (2003-03-01), Ohi
patent: 6539543 (2003-03-01), Guffens
patent: 6574740 (2003-06-01), Odaohhara et al.
patent: 6625740 (2003-09-01), Datar et al.
patent: 6658578 (2003-12-01), Laurenti et al.
patent: 6675305 (2004-01-01), Mohammad
patent: 6687838 (2004-02-01), Orenstien et al.
patent: 6795781 (2004-09-01), Aldridge et al.
patent: 6813693 (2004-11-01), Chilimbi
patent: 6826652 (2004-11-01), Chauvel et al.
patent: 6971092 (2005-11-01), Chilimbi
patent: 6988183 (2006-01-01), Wong
patent: 2001/0044891 (2001-11-01), McGrath et al.
patent: 2001/0056531 (2001-12-01), McFarling
patent: 2002/0116578 (2002-08-01), Sakai et al.
patent: 2004/0010679 (2004-01-01), Moritz et al.
patent: 2004/0010782 (2004-01-01), Moritz et al.
patent: 2004/0015923 (2004-01-01), Hemsing et al.
patent: 2004/0205740 (2004-10-01), Lavery et al.
The standard performance evaluation corporation. http://www.spec.org, Dec. 2000.
D. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. In Proceedings of the 32nd International Symposium on Microarchitecture (MICRO '99), Haifa, Israel, Nov. 1999. ACM Press.
L. Benini, A. Macii, and M. Poncino. A Recursive Algorithm for Low-Power Memory Partitioning. In Proceedings of the International Symposium on Low-Power Electronics (ISLPED '00), Rapallo, Italy, 2000. ACM Press.
D. Brooks, V. Tiwari, and M. Martonosi. Wattach: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA '00), Vancouver, Canada, Jun. 2000. ACM Press.
D. Burger and T. D. Austin. The simplescalar tool set, version 2.0. In University of Wisconsin-Madison Computer-Sciences Department Technical Report #1342, Jun. 1997.
D. Chiou, P. Jain, L. Rudolph, and S. Devdas. Application-specific memory management for embedded systems using software-controlled caches. In Proceedings of the 37th Design Automation Conference (DAC'00), Los Angeles, CA, Jun. 2000. ACM Press.
K. D. Cooper and T. J. Harvey. Compiler-controlled memory. In Proceedings of the 8th International Confernece on Architectural Support for Programming Languages and Systems, Oct. 1998.
C. C. Corporation. Compiler writer's guide for the alpha 21264.
S. Furber et al., ARM3 -32b RISC processor with 4 KByte on-chip cache. In Proceedings of the International Conference on VLSI, Elsevier, North Holland, Aug. 1989.
S. Furber, J. Garside, and S. Temple. Power saving features, in Amulet2e. In Power Driven Microarchitecture Workshop at 25th Annual International Symposium on Computer Architecture, Barcelona, Spain, Jun. 1998.
G. Heinrich. Mips r10000 microprocessor's user manual. Second Edition.
http://web.archive.org/web/20020601014716/http://www.spec.org, The Standard Performance Evaluation Corporation, Dec. 2000, accessed Jun. 14, 2004.
D. Albonesi, “Selective Cache Ways: On-Demand Cache Resource Allocation”, Proceedings of the 32ndInternational Symposium on Microarchitecture, Nov. 1999, Haifa, Israel, ACM Press.
L. Benini et al., “A Recursive Algorithm for Low-Power Memory Partitioning”, Proceedings of the International Symposium on Low-Power Electronics, 2000, Rapallo, Italy, ACM Press.
Brooks et al., “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations”, Proceedings of the 27thInternational Symposium on Computer Architecture, pp. 83-94, Jun. 2000, ACM Press.
D. Burger et al., The simplescalar tool set, version 2.0. In University of Wisconsin-Madison Computer-Sciences Department Technical Report #1342, Jun. 1997.
D. Chiou et al., “Application-specific memory management for embedded systems using software-controlled caches”, Proceedings of the 37th Design Automation Conference (DAC '00), Los Angeles, CA, Jun. 2000. ACM Press.
K. D. Cooper et al., “Compiler-controlled memory”, Proceedings of the 8th International Confernece on Architectural Support for Programming Languages and Systems, Oct. 1998.
http://ftp.digital.com/pub/Digital/info/semiconductor/literature/cmpwrgd.pdf, “Compiler Writer's Guide for the Alpha 21264”, Compaq Computer Corporation, 1999, Digital Equipment Corporation.
S. Furber et al., “ARM3-32b RISC processor with 4 KByte on-chip cache”, Proceedings of the International Conferenece on VLSI, Elsevier, North Holland, Aug. 1989.
S. Furber et al., “Power saving features in Amulet2e”, Power Driven Microarchitecture Workshop at 25th Annual International Symposium on Computer Architecture, Jun. 1998, Barcelona, Spain.
J. Heinrich, MIPS R10000 Microprocessor's User Manual, Second Edition.
J. Heinrich, MIPS R4000 Microprocessor User's Manual, Second Edition, MIPS Technologies, Inc. (1994).
Huang et al., “L1 Data Cache Decomposition for Energy Efficiency”, ISLPED, pp. 10-15 ( 2001).
Inoue et al., “Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption”, ISLPED99, pp. 273-275 (1999).
Kaxiras et al., “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power”, IEEE, pp. 240-251 (2001).
Kin et al., “The Filter Cache: An Energy Efficient Memory Structure”, IEEE, pp. 184-193 (1997).
Lee et al.,“MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems”, pp. 330-335.
Manne et al., “Pipeline Gating: Speculation Control For Energy Reduction”, IEEE, pp. 132-141 (1998).
Memik et al., “Selective Hardware/Compiler Approach for Improving Cache Locality”, Dept. of Computer Science and Engineering, The Pennsylvania University, pp. 1-21.
Montanaro et al., “A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor”, The Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1703-1714 (1996).
Moritz et al., “FlexCache: A Framework for Flexible Compiler Generated Data Caching”, University of Massachusetts, Amherst, MA, M.I.T., Cambridge, MA.
Moritz et al., “Hot Pages: Software Caching for Raw Microprocessors”, (1998), M.I.T., Cambridge, MA.
Pering et al., “Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System”, .
Powell et al., “Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping”, IEEE, pp. 54-65 (2001).
Reinman et al., “An Integrated Cache Timing and Power Model”, C
Ashok Raksit
Chheda Saurabh
Koren Israel
Krishna Mani
Moritz Csaba Andras
Steelman Mary
University of Massachusetts
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